Lines Matching refs:mult
60 unsigned int mult; in cpg_z_clk_recalc_rate() local
64 mult = 32 - val; in cpg_z_clk_recalc_rate()
66 return div_u64((u64)parent_rate * mult, 32); in cpg_z_clk_recalc_rate()
73 unsigned int mult; in cpg_z_clk_round_rate() local
78 mult = div_u64((u64)rate * 32, prate); in cpg_z_clk_round_rate()
79 mult = clamp(mult, 1U, 32U); in cpg_z_clk_round_rate()
81 return *parent_rate / 32 * mult; in cpg_z_clk_round_rate()
88 unsigned int mult; in cpg_z_clk_set_rate() local
92 mult = div_u64((u64)rate * 32, parent_rate); in cpg_z_clk_set_rate()
93 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
100 val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; in cpg_z_clk_set_rate()
176 fixed->mult = 1; in cpg_rcan_clk_register()
315 unsigned int mult = 1; in rcar_gen2_cpg_register_clock() local
329 mult = config->pll0_mult; in rcar_gen2_cpg_register_clock()
333 mult = ((value >> 24) & ((1 << 7) - 1)) + 1; in rcar_gen2_cpg_register_clock()
338 mult = config->pll1_mult / 2; in rcar_gen2_cpg_register_clock()
341 mult = config->pll3_mult; in rcar_gen2_cpg_register_clock()
373 mult, div); in rcar_gen2_cpg_register_clock()