32 						struct clk_fepll, cdiv)
74 	struct clk_regmap_div cdiv;  member
1214 	u32 fdbkdiv, refclkdiv, cdiv;  in clk_fepll_vco_calc_rate()  local
1217 	regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv);  in clk_fepll_vco_calc_rate()
1218 	refclkdiv = (cdiv >> pll_vco->refclkdiv_shift) &  in clk_fepll_vco_calc_rate()
1220 	fdbkdiv = (cdiv >> pll_vco->fdbkdiv_shift) &  in clk_fepll_vco_calc_rate()
1285 	mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift;  in clk_cpu_div_set_rate()
1286 	ret = regmap_update_bits(pll->cdiv.clkr.regmap,  in clk_cpu_div_set_rate()
1287 				 pll->cdiv.reg, mask,  in clk_cpu_div_set_rate()
1288 				 f->pre_div << pll->cdiv.shift);  in clk_cpu_div_set_rate()
1309 	u32 cdiv, pre_div;  in clk_cpu_div_recalc_rate()  local
1312 	regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);  in clk_cpu_div_recalc_rate()
1313 	cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);  in clk_cpu_div_recalc_rate()
1320 	if (cdiv > 10)  in clk_cpu_div_recalc_rate()
1321 		pre_div = (cdiv + 1) * 2;  in clk_cpu_div_recalc_rate()
1323 		pre_div = cdiv + 12;  in clk_cpu_div_recalc_rate()
1356 	.cdiv.reg = 0x2e020,
1357 	.cdiv.shift = 4,
1358 	.cdiv.width = 4,
1359 	.cdiv.clkr = {
1385 	u32 cdiv, pre_div = 1;  in clk_regmap_clk_div_recalc_rate()  local
1392 		regmap_read(pll->cdiv.clkr.regmap, pll->cdiv.reg, &cdiv);  in clk_regmap_clk_div_recalc_rate()
1393 		cdiv = (cdiv >> pll->cdiv.shift) & (BIT(pll->cdiv.width) - 1);  in clk_regmap_clk_div_recalc_rate()
1396 			if (clkt->val == cdiv)  in clk_regmap_clk_div_recalc_rate()
1413 	.cdiv.clkr = {
1428 	.cdiv.clkr = {
1443 	.cdiv.clkr = {
1458 	.cdiv.clkr = {
1473 	.cdiv.clkr = {
1495 	.cdiv.reg = 0x2f020,
1496 	.cdiv.shift = 8,
1497 	.cdiv.width = 2,
1498 	.cdiv.clkr = {
1513 	.cdiv.reg = 0x2f020,
1514 	.cdiv.shift = 12,
1515 	.cdiv.width = 2,
1516 	.cdiv.clkr = {
1627 	[GCC_SDCC_PLLDIV_CLK] = &gcc_apss_sdcc_clk.cdiv.clkr,
1628 	[GCC_FEPLL125_CLK] = &gcc_fepll125_clk.cdiv.clkr,
1629 	[GCC_FEPLL125DLY_CLK] = &gcc_fepll125dly_clk.cdiv.clkr,
1630 	[GCC_FEPLL200_CLK] = &gcc_fepll200_clk.cdiv.clkr,
1631 	[GCC_FEPLL500_CLK] = &gcc_fepll500_clk.cdiv.clkr,
1632 	[GCC_FEPLL_WCSS2G_CLK] = &gcc_fepllwcss2g_clk.cdiv.clkr,
1633 	[GCC_FEPLL_WCSS5G_CLK] = &gcc_fepllwcss5g_clk.cdiv.clkr,
1634 	[GCC_APSS_CPU_PLLDIV_CLK] = &gcc_apss_cpu_plldiv_clk.cdiv.clkr,