47 static DEFINE_SPINLOCK(clk_lock);
159 				ARRAY_SIZE(uart_factor_tbl), &clk_lock);  in pxa168_clk_init()
164 				apbc_base + APBC_TWSI0, 10, 0, &clk_lock);  in pxa168_clk_init()
168 				apbc_base + APBC_TWSI1, 10, 0, &clk_lock);  in pxa168_clk_init()
172 				apbc_base + APBC_GPIO, 10, 0, &clk_lock);  in pxa168_clk_init()
176 				apbc_base + APBC_KPC, 10, 0, &clk_lock);  in pxa168_clk_init()
180 				apbc_base + APBC_RTC, 10, 0, &clk_lock);  in pxa168_clk_init()
184 				apbc_base + APBC_PWM0, 10, 0, &clk_lock);  in pxa168_clk_init()
188 				apbc_base + APBC_PWM1, 10, 0, &clk_lock);  in pxa168_clk_init()
192 				apbc_base + APBC_PWM2, 10, 0, &clk_lock);  in pxa168_clk_init()
196 				apbc_base + APBC_PWM3, 10, 0, &clk_lock);  in pxa168_clk_init()
202 				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
207 				apbc_base + APBC_UART0, 10, 0, &clk_lock);  in pxa168_clk_init()
213 				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
218 				apbc_base + APBC_UART1,	10, 0, &clk_lock);  in pxa168_clk_init()
224 				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
229 				apbc_base + APBC_UART2,	10, 0, &clk_lock);  in pxa168_clk_init()
235 				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
239 				10, 0, &clk_lock);  in pxa168_clk_init()
245 				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
249 				10, 0, &clk_lock);  in pxa168_clk_init()
255 				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
259 				10, 0, &clk_lock);  in pxa168_clk_init()
265 				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
269 				10, 0, &clk_lock);  in pxa168_clk_init()
275 				apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);  in pxa168_clk_init()
279 				10, 0, &clk_lock);  in pxa168_clk_init()
283 				0x19b, &clk_lock);  in pxa168_clk_init()
289 				apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
293 				0x1b, &clk_lock);  in pxa168_clk_init()
299 				apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
303 				0x1b, &clk_lock);  in pxa168_clk_init()
307 				0x9, &clk_lock);  in pxa168_clk_init()
311 				0x12, &clk_lock);  in pxa168_clk_init()
317 				apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
321 				apmu_base + APMU_DISP0, 0x1b, &clk_lock);  in pxa168_clk_init()
325 				apmu_base + APMU_DISP0, 0x24, &clk_lock);  in pxa168_clk_init()
331 				apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);  in pxa168_clk_init()
335 				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);  in pxa168_clk_init()
341 				apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);  in pxa168_clk_init()
345 				apmu_base + APMU_CCIC0, 0x24, &clk_lock);  in pxa168_clk_init()
350 				10, 5, 0, &clk_lock);  in pxa168_clk_init()
354 				apmu_base + APMU_CCIC0, 0x300, &clk_lock);  in pxa168_clk_init()