Lines Matching full:hw
62 .hw.init = &(struct clk_init_data){
79 .hw.init = &(struct clk_init_data){
83 &g12a_fixed_pll_dco.hw
127 .hw.init = &(struct clk_init_data){
146 .hw.init = &(struct clk_init_data){
150 &g12a_sys_pll_dco.hw
186 .hw.init = &(struct clk_init_data){
205 .hw.init = &(struct clk_init_data){
209 &g12b_sys1_pll_dco.hw
221 .hw.init = &(struct clk_init_data) {
224 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
238 .hw.init = &(struct clk_init_data) {
242 &g12b_sys1_pll.hw
255 .hw.init = &(struct clk_init_data){
259 &g12a_sys_pll_div16_en.hw
268 .hw.init = &(struct clk_init_data){
272 &g12b_sys1_pll_div16_en.hw
281 .hw.init = &(struct clk_init_data){
284 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
294 .hw.init = &(struct clk_init_data){
298 &g12a_fclk_div2_div.hw
307 .hw.init = &(struct clk_init_data){
310 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
320 .hw.init = &(struct clk_init_data){
324 &g12a_fclk_div3_div.hw
348 .hw.init = &(struct clk_init_data){
353 { .hw = &g12a_fclk_div2.hw },
354 { .hw = &g12a_fclk_div3.hw },
368 .hw.init = &(struct clk_init_data){
373 { .hw = &g12a_fclk_div2.hw },
374 { .hw = &g12a_fclk_div3.hw },
396 .hw.init = &(struct clk_init_data){
400 &g12a_cpu_clk_premux0.hw
415 .hw.init = &(struct clk_init_data){
419 &g12a_cpu_clk_premux0.hw,
420 &g12a_cpu_clk_mux0_div.hw,
434 .hw.init = &(struct clk_init_data){
438 &g12a_cpu_clk_premux1.hw
451 .hw.init = &(struct clk_init_data){
455 &g12a_cpu_clk_premux1.hw,
456 &g12a_cpu_clk_mux1_div.hw,
472 .hw.init = &(struct clk_init_data){
476 &g12a_cpu_clk_postmux0.hw,
477 &g12a_cpu_clk_postmux1.hw,
492 .hw.init = &(struct clk_init_data){
496 &g12a_cpu_clk_dyn.hw,
497 &g12a_sys_pll.hw,
512 .hw.init = &(struct clk_init_data){
516 &g12a_cpu_clk_dyn.hw,
517 &g12b_sys1_pll.hw
532 .hw.init = &(struct clk_init_data){
537 { .hw = &g12a_fclk_div2.hw },
538 { .hw = &g12a_fclk_div3.hw },
559 .hw.init = &(struct clk_init_data){
563 &g12b_cpub_clk_premux0.hw
578 .hw.init = &(struct clk_init_data){
582 &g12b_cpub_clk_premux0.hw,
583 &g12b_cpub_clk_mux0_div.hw
597 .hw.init = &(struct clk_init_data){
602 { .hw = &g12a_fclk_div2.hw },
603 { .hw = &g12a_fclk_div3.hw },
618 .hw.init = &(struct clk_init_data){
622 &g12b_cpub_clk_premux1.hw
635 .hw.init = &(struct clk_init_data){
639 &g12b_cpub_clk_premux1.hw,
640 &g12b_cpub_clk_mux1_div.hw
656 .hw.init = &(struct clk_init_data){
660 &g12b_cpub_clk_postmux0.hw,
661 &g12b_cpub_clk_postmux1.hw
676 .hw.init = &(struct clk_init_data){
680 &g12b_cpub_clk_dyn.hw,
681 &g12a_sys_pll.hw
697 .hw.init = &(struct clk_init_data){
702 { .hw = &g12a_fclk_div2.hw },
703 { .hw = &g12a_fclk_div3.hw },
704 { .hw = &sm1_gp1_pll.hw },
717 .hw.init = &(struct clk_init_data){
722 { .hw = &g12a_fclk_div2.hw },
723 { .hw = &g12a_fclk_div3.hw },
724 { .hw = &sm1_gp1_pll.hw },
737 .hw.init = &(struct clk_init_data){
741 &sm1_dsu_clk_premux0.hw
754 .hw.init = &(struct clk_init_data){
758 &sm1_dsu_clk_premux0.hw,
759 &sm1_dsu_clk_mux0_div.hw,
772 .hw.init = &(struct clk_init_data){
776 &sm1_dsu_clk_premux1.hw
789 .hw.init = &(struct clk_init_data){
793 &sm1_dsu_clk_premux1.hw,
794 &sm1_dsu_clk_mux1_div.hw,
807 .hw.init = &(struct clk_init_data){
811 &sm1_dsu_clk_postmux0.hw,
812 &sm1_dsu_clk_postmux1.hw,
825 .hw.init = &(struct clk_init_data){
829 &sm1_dsu_clk_dyn.hw,
830 &g12a_sys_pll.hw,
843 .hw.init = &(struct clk_init_data){
847 &g12a_cpu_clk.hw,
861 .hw.init = &(struct clk_init_data){
865 &g12a_cpu_clk.hw,
879 .hw.init = &(struct clk_init_data){
883 &g12a_cpu_clk.hw,
897 .hw.init = &(struct clk_init_data){
901 &g12a_cpu_clk.hw,
902 &sm1_dsu_final_clk.hw,
1014 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1015 .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1016 .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1017 .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1022 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1023 .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1024 .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1025 .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1097 .sys_pll = &g12a_sys_pll.hw,
1098 .cpu_clk = &g12a_cpu_clk.hw,
1099 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1105 .sys_pll = &g12b_sys1_pll.hw,
1106 .cpu_clk = &g12b_cpu_clk.hw,
1107 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1113 .sys_pll = &g12a_sys_pll.hw,
1114 .cpu_clk = &g12b_cpub_clk.hw,
1115 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1124 .hw.init = &(struct clk_init_data) {
1128 &g12a_cpu_clk.hw
1143 .hw.init = &(struct clk_init_data) {
1147 &g12b_cpub_clk.hw
1160 .hw.init = &(struct clk_init_data){
1164 &g12a_cpu_clk_div16_en.hw
1173 .hw.init = &(struct clk_init_data){
1177 &g12b_cpub_clk_div16_en.hw
1190 .hw.init = &(struct clk_init_data){
1193 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1203 .hw.init = &(struct clk_init_data) {
1207 &g12a_cpu_clk_apb_div.hw
1224 .hw.init = &(struct clk_init_data){
1227 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1237 .hw.init = &(struct clk_init_data) {
1241 &g12a_cpu_clk_atb_div.hw
1258 .hw.init = &(struct clk_init_data){
1261 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1271 .hw.init = &(struct clk_init_data) {
1275 &g12a_cpu_clk_axi_div.hw
1292 .hw.init = &(struct clk_init_data){
1315 .hw.init = &(struct clk_init_data) {
1319 &g12a_cpu_clk_trace_div.hw
1332 .hw.init = &(struct clk_init_data){
1336 &g12b_cpub_clk.hw
1345 .hw.init = &(struct clk_init_data){
1349 &g12b_cpub_clk.hw
1358 .hw.init = &(struct clk_init_data){
1362 &g12b_cpub_clk.hw
1371 .hw.init = &(struct clk_init_data){
1375 &g12b_cpub_clk.hw
1384 .hw.init = &(struct clk_init_data){
1388 &g12b_cpub_clk.hw
1397 .hw.init = &(struct clk_init_data){
1401 &g12b_cpub_clk.hw
1410 .hw.init = &(struct clk_init_data){
1414 &g12b_cpub_clk.hw
1428 .hw.init = &(struct clk_init_data){
1432 &g12b_cpub_clk_div2.hw,
1433 &g12b_cpub_clk_div3.hw,
1434 &g12b_cpub_clk_div4.hw,
1435 &g12b_cpub_clk_div5.hw,
1436 &g12b_cpub_clk_div6.hw,
1437 &g12b_cpub_clk_div7.hw,
1438 &g12b_cpub_clk_div8.hw
1450 .hw.init = &(struct clk_init_data) {
1454 &g12b_cpub_clk_apb_sel.hw
1471 .hw.init = &(struct clk_init_data){
1475 &g12b_cpub_clk_div2.hw,
1476 &g12b_cpub_clk_div3.hw,
1477 &g12b_cpub_clk_div4.hw,
1478 &g12b_cpub_clk_div5.hw,
1479 &g12b_cpub_clk_div6.hw,
1480 &g12b_cpub_clk_div7.hw,
1481 &g12b_cpub_clk_div8.hw
1493 .hw.init = &(struct clk_init_data) {
1497 &g12b_cpub_clk_atb_sel.hw
1514 .hw.init = &(struct clk_init_data){
1518 &g12b_cpub_clk_div2.hw,
1519 &g12b_cpub_clk_div3.hw,
1520 &g12b_cpub_clk_div4.hw,
1521 &g12b_cpub_clk_div5.hw,
1522 &g12b_cpub_clk_div6.hw,
1523 &g12b_cpub_clk_div7.hw,
1524 &g12b_cpub_clk_div8.hw
1536 .hw.init = &(struct clk_init_data) {
1540 &g12b_cpub_clk_axi_sel.hw
1557 .hw.init = &(struct clk_init_data){
1561 &g12b_cpub_clk_div2.hw,
1562 &g12b_cpub_clk_div3.hw,
1563 &g12b_cpub_clk_div4.hw,
1564 &g12b_cpub_clk_div5.hw,
1565 &g12b_cpub_clk_div6.hw,
1566 &g12b_cpub_clk_div7.hw,
1567 &g12b_cpub_clk_div8.hw
1579 .hw.init = &(struct clk_init_data) {
1583 &g12b_cpub_clk_trace_sel.hw
1646 .hw.init = &(struct clk_init_data){
1664 .hw.init = &(struct clk_init_data){
1668 &g12a_gp0_pll_dco.hw
1708 .hw.init = &(struct clk_init_data){
1728 .hw.init = &(struct clk_init_data){
1732 &sm1_gp1_pll_dco.hw
1787 .hw.init = &(struct clk_init_data){
1805 .hw.init = &(struct clk_init_data){
1809 &g12a_hifi_pll_dco.hw
1878 .hw.init = &(struct clk_init_data){
1891 .hw.init = &(struct clk_init_data){
1895 &g12a_pcie_pll_dco.hw
1911 .hw.init = &(struct clk_init_data){
1915 &g12a_pcie_pll_dco_div2.hw
1925 .hw.init = &(struct clk_init_data){
1929 &g12a_pcie_pll_od.hw
1969 .hw.init = &(struct clk_init_data){
1991 .hw.init = &(struct clk_init_data){
1995 &g12a_hdmi_pll_dco.hw
2009 .hw.init = &(struct clk_init_data){
2013 &g12a_hdmi_pll_od.hw
2027 .hw.init = &(struct clk_init_data){
2031 &g12a_hdmi_pll_od2.hw
2041 .hw.init = &(struct clk_init_data){
2044 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2054 .hw.init = &(struct clk_init_data){
2058 &g12a_fclk_div4_div.hw
2067 .hw.init = &(struct clk_init_data){
2070 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2080 .hw.init = &(struct clk_init_data){
2084 &g12a_fclk_div5_div.hw
2093 .hw.init = &(struct clk_init_data){
2096 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2106 .hw.init = &(struct clk_init_data){
2110 &g12a_fclk_div7_div.hw
2119 .hw.init = &(struct clk_init_data){
2123 &g12a_fixed_pll_dco.hw
2134 .hw.init = &(struct clk_init_data){
2138 &g12a_fclk_div2p5_div.hw
2147 .hw.init = &(struct clk_init_data){
2151 &g12a_fixed_pll_dco.hw
2163 .hw.init = &(struct clk_init_data){
2168 { .hw = &g12a_mpll_50m_div.hw },
2177 .hw.init = &(struct clk_init_data){
2181 &g12a_fixed_pll_dco.hw
2217 .hw.init = &(struct clk_init_data){
2221 &g12a_mpll_prediv.hw
2232 .hw.init = &(struct clk_init_data){
2235 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2271 .hw.init = &(struct clk_init_data){
2275 &g12a_mpll_prediv.hw
2286 .hw.init = &(struct clk_init_data){
2289 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2325 .hw.init = &(struct clk_init_data){
2329 &g12a_mpll_prediv.hw
2340 .hw.init = &(struct clk_init_data){
2343 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2379 .hw.init = &(struct clk_init_data){
2383 &g12a_mpll_prediv.hw
2394 .hw.init = &(struct clk_init_data){
2397 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2406 { .hw = &g12a_fclk_div7.hw },
2407 { .hw = &g12a_mpll1.hw },
2408 { .hw = &g12a_mpll2.hw },
2409 { .hw = &g12a_fclk_div4.hw },
2410 { .hw = &g12a_fclk_div3.hw },
2411 { .hw = &g12a_fclk_div5.hw },
2421 .hw.init = &(struct clk_init_data){
2435 .hw.init = &(struct clk_init_data){
2439 &g12a_mpeg_clk_sel.hw
2451 .hw.init = &(struct clk_init_data){
2455 &g12a_mpeg_clk_div.hw
2464 { .hw = &g12a_fclk_div2.hw },
2465 { .hw = &g12a_fclk_div3.hw },
2466 { .hw = &g12a_fclk_div5.hw },
2467 { .hw = &g12a_fclk_div7.hw },
2483 .hw.init = &(struct clk_init_data) {
2498 .hw.init = &(struct clk_init_data) {
2502 &g12a_sd_emmc_a_clk0_sel.hw
2514 .hw.init = &(struct clk_init_data){
2518 &g12a_sd_emmc_a_clk0_div.hw
2532 .hw.init = &(struct clk_init_data) {
2547 .hw.init = &(struct clk_init_data) {
2551 &g12a_sd_emmc_b_clk0_sel.hw
2563 .hw.init = &(struct clk_init_data){
2567 &g12a_sd_emmc_b_clk0_div.hw
2581 .hw.init = &(struct clk_init_data) {
2596 .hw.init = &(struct clk_init_data) {
2600 &g12a_sd_emmc_c_clk0_sel.hw
2612 .hw.init = &(struct clk_init_data){
2616 &g12a_sd_emmc_c_clk0_div.hw
2638 .hw.init = &(struct clk_init_data) {
2641 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2648 &g12a_vid_pll_div.hw,
2649 &g12a_hdmi_pll.hw,
2658 .hw.init = &(struct clk_init_data){
2676 .hw.init = &(struct clk_init_data) {
2680 &g12a_vid_pll_sel.hw
2690 &g12a_fclk_div3.hw,
2691 &g12a_fclk_div4.hw,
2692 &g12a_fclk_div5.hw,
2693 &g12a_fclk_div7.hw,
2694 &g12a_mpll1.hw,
2695 &g12a_vid_pll.hw,
2696 &g12a_hifi_pll.hw,
2697 &g12a_gp0_pll.hw,
2706 .hw.init = &(struct clk_init_data){
2721 .hw.init = &(struct clk_init_data){
2724 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2735 .hw.init = &(struct clk_init_data) {
2738 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2750 .hw.init = &(struct clk_init_data){
2765 .hw.init = &(struct clk_init_data){
2768 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2779 .hw.init = &(struct clk_init_data) {
2782 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2794 .hw.init = &(struct clk_init_data){
2802 &g12a_vpu_0.hw,
2803 &g12a_vpu_1.hw,
2813 &g12a_fclk_div2p5.hw,
2814 &g12a_fclk_div3.hw,
2815 &g12a_fclk_div4.hw,
2816 &g12a_fclk_div5.hw,
2817 &g12a_fclk_div7.hw,
2818 &g12a_hifi_pll.hw,
2819 &g12a_gp0_pll.hw,
2829 .hw.init = &(struct clk_init_data){
2845 .hw.init = &(struct clk_init_data){
2849 &g12a_vdec_1_sel.hw
2861 .hw.init = &(struct clk_init_data) {
2865 &g12a_vdec_1_div.hw
2879 .hw.init = &(struct clk_init_data){
2895 .hw.init = &(struct clk_init_data){
2899 &g12a_vdec_hevcf_sel.hw
2911 .hw.init = &(struct clk_init_data) {
2915 &g12a_vdec_hevcf_div.hw
2929 .hw.init = &(struct clk_init_data){
2945 .hw.init = &(struct clk_init_data){
2949 &g12a_vdec_hevc_sel.hw
2961 .hw.init = &(struct clk_init_data) {
2965 &g12a_vdec_hevc_div.hw
2975 &g12a_fclk_div4.hw,
2976 &g12a_fclk_div3.hw,
2977 &g12a_fclk_div5.hw,
2978 &g12a_fclk_div7.hw,
2979 &g12a_mpll1.hw,
2980 &g12a_vid_pll.hw,
2981 &g12a_mpll2.hw,
2982 &g12a_fclk_div2p5.hw,
2991 .hw.init = &(struct clk_init_data){
3006 .hw.init = &(struct clk_init_data){
3010 &g12a_vapb_0_sel.hw
3022 .hw.init = &(struct clk_init_data) {
3026 &g12a_vapb_0_div.hw
3039 .hw.init = &(struct clk_init_data){
3054 .hw.init = &(struct clk_init_data){
3058 &g12a_vapb_1_sel.hw
3070 .hw.init = &(struct clk_init_data) {
3074 &g12a_vapb_1_div.hw
3087 .hw.init = &(struct clk_init_data){
3095 &g12a_vapb_0.hw,
3096 &g12a_vapb_1.hw,
3108 .hw.init = &(struct clk_init_data) {
3111 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3118 &g12a_vid_pll.hw,
3119 &g12a_gp0_pll.hw,
3120 &g12a_hifi_pll.hw,
3121 &g12a_mpll1.hw,
3122 &g12a_fclk_div3.hw,
3123 &g12a_fclk_div4.hw,
3124 &g12a_fclk_div5.hw,
3125 &g12a_fclk_div7.hw,
3134 .hw.init = &(struct clk_init_data){
3149 .hw.init = &(struct clk_init_data){
3163 .hw.init = &(struct clk_init_data) {
3166 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3177 .hw.init = &(struct clk_init_data) {
3180 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3192 .hw.init = &(struct clk_init_data){
3196 &g12a_vclk_input.hw
3209 .hw.init = &(struct clk_init_data){
3213 &g12a_vclk2_input.hw
3225 .hw.init = &(struct clk_init_data) {
3228 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3239 .hw.init = &(struct clk_init_data) {
3242 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3253 .hw.init = &(struct clk_init_data) {
3256 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3267 .hw.init = &(struct clk_init_data) {
3270 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3281 .hw.init = &(struct clk_init_data) {
3284 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3295 .hw.init = &(struct clk_init_data) {
3298 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3309 .hw.init = &(struct clk_init_data) {
3312 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3323 .hw.init = &(struct clk_init_data) {
3326 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3337 .hw.init = &(struct clk_init_data) {
3340 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3351 .hw.init = &(struct clk_init_data) {
3354 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3365 .hw.init = &(struct clk_init_data) {
3368 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3379 .hw.init = &(struct clk_init_data) {
3382 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3391 .hw.init = &(struct clk_init_data){
3395 &g12a_vclk_div2_en.hw
3404 .hw.init = &(struct clk_init_data){
3408 &g12a_vclk_div4_en.hw
3417 .hw.init = &(struct clk_init_data){
3421 &g12a_vclk_div6_en.hw
3430 .hw.init = &(struct clk_init_data){
3434 &g12a_vclk_div12_en.hw
3443 .hw.init = &(struct clk_init_data){
3447 &g12a_vclk2_div2_en.hw
3456 .hw.init = &(struct clk_init_data){
3460 &g12a_vclk2_div4_en.hw
3469 .hw.init = &(struct clk_init_data){
3473 &g12a_vclk2_div6_en.hw
3482 .hw.init = &(struct clk_init_data){
3486 &g12a_vclk2_div12_en.hw
3494 &g12a_vclk_div1.hw,
3495 &g12a_vclk_div2.hw,
3496 &g12a_vclk_div4.hw,
3497 &g12a_vclk_div6.hw,
3498 &g12a_vclk_div12.hw,
3499 &g12a_vclk2_div1.hw,
3500 &g12a_vclk2_div2.hw,
3501 &g12a_vclk2_div4.hw,
3502 &g12a_vclk2_div6.hw,
3503 &g12a_vclk2_div12.hw,
3513 .hw.init = &(struct clk_init_data){
3529 .hw.init = &(struct clk_init_data){
3545 .hw.init = &(struct clk_init_data){
3557 &g12a_vclk_div1.hw,
3558 &g12a_vclk_div2.hw,
3559 &g12a_vclk_div4.hw,
3560 &g12a_vclk_div6.hw,
3561 &g12a_vclk_div12.hw,
3562 &g12a_vclk2_div1.hw,
3563 &g12a_vclk2_div2.hw,
3564 &g12a_vclk2_div4.hw,
3565 &g12a_vclk2_div6.hw,
3566 &g12a_vclk2_div12.hw,
3576 .hw.init = &(struct clk_init_data){
3590 .hw.init = &(struct clk_init_data) {
3594 &g12a_cts_enci_sel.hw
3606 .hw.init = &(struct clk_init_data) {
3610 &g12a_cts_encp_sel.hw
3622 .hw.init = &(struct clk_init_data) {
3626 &g12a_cts_vdac_sel.hw
3638 .hw.init = &(struct clk_init_data) {
3642 &g12a_hdmi_tx_sel.hw
3653 { .hw = &g12a_fclk_div4.hw },
3654 { .hw = &g12a_fclk_div3.hw },
3655 { .hw = &g12a_fclk_div5.hw },
3665 .hw.init = &(struct clk_init_data){
3680 .hw.init = &(struct clk_init_data){
3683 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3694 .hw.init = &(struct clk_init_data) {
3697 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3709 { .hw = &g12a_gp0_pll.hw },
3710 { .hw = &g12a_hifi_pll.hw },
3711 { .hw = &g12a_fclk_div2p5.hw },
3712 { .hw = &g12a_fclk_div3.hw },
3713 { .hw = &g12a_fclk_div4.hw },
3714 { .hw = &g12a_fclk_div5.hw },
3715 { .hw = &g12a_fclk_div7.hw },
3724 .hw.init = &(struct clk_init_data){
3739 .hw.init = &(struct clk_init_data){
3743 &g12a_mali_0_sel.hw
3755 .hw.init = &(struct clk_init_data){
3759 &g12a_mali_0_div.hw
3772 .hw.init = &(struct clk_init_data){
3787 .hw.init = &(struct clk_init_data){
3791 &g12a_mali_1_sel.hw
3803 .hw.init = &(struct clk_init_data){
3807 &g12a_mali_1_div.hw
3815 &g12a_mali_0.hw,
3816 &g12a_mali_1.hw,
3825 .hw.init = &(struct clk_init_data){
3840 .hw.init = &(struct clk_init_data){
3855 .hw.init = &(struct clk_init_data){
3859 &g12a_ts_div.hw
3866 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
3869 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
3949 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
3950 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
3951 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
3952 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
3953 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
3954 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
3955 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
3956 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
3957 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
3958 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
3959 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
3960 [CLKID_CLK81] = &g12a_clk81.hw,
3961 [CLKID_MPLL0] = &g12a_mpll0.hw,
3962 [CLKID_MPLL1] = &g12a_mpll1.hw,
3963 [CLKID_MPLL2] = &g12a_mpll2.hw,
3964 [CLKID_MPLL3] = &g12a_mpll3.hw,
3965 [CLKID_DDR] = &g12a_ddr.hw,
3966 [CLKID_DOS] = &g12a_dos.hw,
3967 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
3968 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
3969 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
3970 [CLKID_ISA] = &g12a_isa.hw,
3971 [CLKID_PL301] = &g12a_pl301.hw,
3972 [CLKID_PERIPHS] = &g12a_periphs.hw,
3973 [CLKID_SPICC0] = &g12a_spicc_0.hw,
3974 [CLKID_I2C] = &g12a_i2c.hw,
3975 [CLKID_SANA] = &g12a_sana.hw,
3976 [CLKID_SD] = &g12a_sd.hw,
3977 [CLKID_RNG0] = &g12a_rng0.hw,
3978 [CLKID_UART0] = &g12a_uart0.hw,
3979 [CLKID_SPICC1] = &g12a_spicc_1.hw,
3980 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
3981 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
3982 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
3983 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
3984 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
3985 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
3986 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
3987 [CLKID_AUDIO] = &g12a_audio.hw,
3988 [CLKID_ETH] = &g12a_eth_core.hw,
3989 [CLKID_DEMUX] = &g12a_demux.hw,
3990 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
3991 [CLKID_ADC] = &g12a_adc.hw,
3992 [CLKID_UART1] = &g12a_uart1.hw,
3993 [CLKID_G2D] = &g12a_g2d.hw,
3994 [CLKID_RESET] = &g12a_reset.hw,
3995 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
3996 [CLKID_PARSER] = &g12a_parser.hw,
3997 [CLKID_USB] = &g12a_usb_general.hw,
3998 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
3999 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4000 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4001 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4002 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4003 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4004 [CLKID_BT656] = &g12a_bt656.hw,
4005 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4006 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4007 [CLKID_UART2] = &g12a_uart2.hw,
4008 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4009 [CLKID_GIC] = &g12a_gic.hw,
4010 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4011 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4012 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4013 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4014 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4015 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4016 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4017 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4018 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4019 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4020 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4021 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4022 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4023 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4024 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4025 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4026 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4027 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4028 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4029 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4030 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4031 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4032 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4033 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4034 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4035 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4036 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4037 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4038 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4039 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4040 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4041 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4042 [CLKID_ENC480P] = &g12a_enc480p.hw,
4043 [CLKID_RNG1] = &g12a_rng1.hw,
4044 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4045 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4046 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4047 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4048 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4049 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4050 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4051 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4052 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4053 [CLKID_DMA] = &g12a_dma.hw,
4054 [CLKID_EFUSE] = &g12a_efuse.hw,
4055 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4056 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4057 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4058 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4059 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4060 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4061 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4062 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4063 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4064 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4065 [CLKID_VPU] = &g12a_vpu.hw,
4066 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4067 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4068 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4069 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4070 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4071 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4072 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4073 [CLKID_VAPB] = &g12a_vapb.hw,
4074 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4075 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4076 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4077 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4078 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4079 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4080 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4081 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4082 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4083 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4084 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4085 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4086 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4087 [CLKID_VCLK] = &g12a_vclk.hw,
4088 [CLKID_VCLK2] = &g12a_vclk2.hw,
4089 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4090 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4091 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4092 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4093 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4094 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4095 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4096 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4097 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4098 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4099 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4100 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4101 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4102 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4103 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4104 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4105 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4106 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4107 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4108 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4109 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4110 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4111 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4112 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4113 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4114 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4115 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4116 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4117 [CLKID_HDMI] = &g12a_hdmi.hw,
4118 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4119 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4120 [CLKID_MALI_0] = &g12a_mali_0.hw,
4121 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4122 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4123 [CLKID_MALI_1] = &g12a_mali_1.hw,
4124 [CLKID_MALI] = &g12a_mali.hw,
4125 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4126 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4127 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4128 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4129 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4130 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4131 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4132 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4133 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4134 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4135 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4136 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4137 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4138 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4139 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4140 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4141 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4142 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4143 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4144 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4145 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4146 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4147 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4148 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4149 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4150 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4151 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4152 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4153 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4154 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4155 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4156 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4157 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4158 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4159 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4160 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4161 [CLKID_TS] = &g12a_ts.hw,
4169 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4170 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4171 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4172 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4173 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4174 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4175 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4176 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4177 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4178 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4179 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4180 [CLKID_CLK81] = &g12a_clk81.hw,
4181 [CLKID_MPLL0] = &g12a_mpll0.hw,
4182 [CLKID_MPLL1] = &g12a_mpll1.hw,
4183 [CLKID_MPLL2] = &g12a_mpll2.hw,
4184 [CLKID_MPLL3] = &g12a_mpll3.hw,
4185 [CLKID_DDR] = &g12a_ddr.hw,
4186 [CLKID_DOS] = &g12a_dos.hw,
4187 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4188 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4189 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4190 [CLKID_ISA] = &g12a_isa.hw,
4191 [CLKID_PL301] = &g12a_pl301.hw,
4192 [CLKID_PERIPHS] = &g12a_periphs.hw,
4193 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4194 [CLKID_I2C] = &g12a_i2c.hw,
4195 [CLKID_SANA] = &g12a_sana.hw,
4196 [CLKID_SD] = &g12a_sd.hw,
4197 [CLKID_RNG0] = &g12a_rng0.hw,
4198 [CLKID_UART0] = &g12a_uart0.hw,
4199 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4200 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4201 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4202 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4203 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4204 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4205 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4206 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4207 [CLKID_AUDIO] = &g12a_audio.hw,
4208 [CLKID_ETH] = &g12a_eth_core.hw,
4209 [CLKID_DEMUX] = &g12a_demux.hw,
4210 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4211 [CLKID_ADC] = &g12a_adc.hw,
4212 [CLKID_UART1] = &g12a_uart1.hw,
4213 [CLKID_G2D] = &g12a_g2d.hw,
4214 [CLKID_RESET] = &g12a_reset.hw,
4215 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4216 [CLKID_PARSER] = &g12a_parser.hw,
4217 [CLKID_USB] = &g12a_usb_general.hw,
4218 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4219 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4220 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4221 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4222 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4223 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4224 [CLKID_BT656] = &g12a_bt656.hw,
4225 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4226 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4227 [CLKID_UART2] = &g12a_uart2.hw,
4228 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4229 [CLKID_GIC] = &g12a_gic.hw,
4230 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4231 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4232 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4233 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4234 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4235 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4236 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4237 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4238 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4239 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4240 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4241 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4242 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4243 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4244 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4245 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4246 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4247 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4248 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4249 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4250 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4251 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4252 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4253 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4254 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4255 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4256 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4257 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4258 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4259 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4260 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4261 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4262 [CLKID_ENC480P] = &g12a_enc480p.hw,
4263 [CLKID_RNG1] = &g12a_rng1.hw,
4264 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4265 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4266 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4267 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4268 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4269 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4270 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4271 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4272 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4273 [CLKID_DMA] = &g12a_dma.hw,
4274 [CLKID_EFUSE] = &g12a_efuse.hw,
4275 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4276 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4277 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4278 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4279 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4280 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4281 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4282 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4283 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4284 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4285 [CLKID_VPU] = &g12a_vpu.hw,
4286 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4287 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4288 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4289 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4290 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4291 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4292 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4293 [CLKID_VAPB] = &g12a_vapb.hw,
4294 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4295 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4296 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4297 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4298 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4299 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4300 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4301 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4302 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4303 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4304 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4305 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4306 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4307 [CLKID_VCLK] = &g12a_vclk.hw,
4308 [CLKID_VCLK2] = &g12a_vclk2.hw,
4309 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4310 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4311 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4312 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4313 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4314 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4315 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4316 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4317 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4318 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4319 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4320 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4321 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4322 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4323 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4324 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4325 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4326 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4327 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4328 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4329 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4330 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4331 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4332 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4333 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4334 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4335 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4336 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4337 [CLKID_HDMI] = &g12a_hdmi.hw,
4338 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4339 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4340 [CLKID_MALI_0] = &g12a_mali_0.hw,
4341 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4342 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4343 [CLKID_MALI_1] = &g12a_mali_1.hw,
4344 [CLKID_MALI] = &g12a_mali.hw,
4345 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4346 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4347 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4348 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4349 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4350 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4351 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4352 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4353 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4354 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4355 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4356 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4357 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4358 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4359 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4360 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4361 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4362 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4363 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4364 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4365 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4366 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4367 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4368 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4369 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4370 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4371 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4372 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4373 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4374 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4375 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4376 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4377 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4378 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4379 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4380 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4381 [CLKID_TS] = &g12a_ts.hw,
4382 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
4383 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4384 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4385 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4386 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
4387 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
4388 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
4389 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
4390 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
4391 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
4392 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4393 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4394 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
4395 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
4396 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
4397 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
4398 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
4399 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
4400 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
4401 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
4402 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
4403 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
4404 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
4405 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
4406 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
4407 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
4408 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
4409 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
4410 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4418 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4419 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4420 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4421 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4422 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4423 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4424 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4425 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4426 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4427 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4428 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4429 [CLKID_CLK81] = &g12a_clk81.hw,
4430 [CLKID_MPLL0] = &g12a_mpll0.hw,
4431 [CLKID_MPLL1] = &g12a_mpll1.hw,
4432 [CLKID_MPLL2] = &g12a_mpll2.hw,
4433 [CLKID_MPLL3] = &g12a_mpll3.hw,
4434 [CLKID_DDR] = &g12a_ddr.hw,
4435 [CLKID_DOS] = &g12a_dos.hw,
4436 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4437 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4438 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4439 [CLKID_ISA] = &g12a_isa.hw,
4440 [CLKID_PL301] = &g12a_pl301.hw,
4441 [CLKID_PERIPHS] = &g12a_periphs.hw,
4442 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4443 [CLKID_I2C] = &g12a_i2c.hw,
4444 [CLKID_SANA] = &g12a_sana.hw,
4445 [CLKID_SD] = &g12a_sd.hw,
4446 [CLKID_RNG0] = &g12a_rng0.hw,
4447 [CLKID_UART0] = &g12a_uart0.hw,
4448 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4449 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4450 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4451 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4452 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4453 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4454 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4455 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4456 [CLKID_AUDIO] = &g12a_audio.hw,
4457 [CLKID_ETH] = &g12a_eth_core.hw,
4458 [CLKID_DEMUX] = &g12a_demux.hw,
4459 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4460 [CLKID_ADC] = &g12a_adc.hw,
4461 [CLKID_UART1] = &g12a_uart1.hw,
4462 [CLKID_G2D] = &g12a_g2d.hw,
4463 [CLKID_RESET] = &g12a_reset.hw,
4464 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4465 [CLKID_PARSER] = &g12a_parser.hw,
4466 [CLKID_USB] = &g12a_usb_general.hw,
4467 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4468 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4469 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4470 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4471 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4472 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4473 [CLKID_BT656] = &g12a_bt656.hw,
4474 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4475 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4476 [CLKID_UART2] = &g12a_uart2.hw,
4477 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4478 [CLKID_GIC] = &g12a_gic.hw,
4479 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4480 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4481 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4482 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4483 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4484 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4485 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4486 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4487 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4488 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4489 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4490 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4491 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4492 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4493 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4494 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4495 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4496 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4497 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4498 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4499 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4500 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4501 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4502 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4503 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4504 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4505 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4506 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4507 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4508 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4509 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4510 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4511 [CLKID_ENC480P] = &g12a_enc480p.hw,
4512 [CLKID_RNG1] = &g12a_rng1.hw,
4513 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4514 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4515 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4516 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4517 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4518 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4519 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4520 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4521 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4522 [CLKID_DMA] = &g12a_dma.hw,
4523 [CLKID_EFUSE] = &g12a_efuse.hw,
4524 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4525 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4526 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4527 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4528 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4529 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4530 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4531 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4532 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4533 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4534 [CLKID_VPU] = &g12a_vpu.hw,
4535 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4536 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4537 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4538 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4539 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4540 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4541 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4542 [CLKID_VAPB] = &g12a_vapb.hw,
4543 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4544 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4545 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4546 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4547 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4548 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4549 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4550 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4551 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4552 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4553 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4554 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4555 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4556 [CLKID_VCLK] = &g12a_vclk.hw,
4557 [CLKID_VCLK2] = &g12a_vclk2.hw,
4558 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4559 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4560 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4561 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4562 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4563 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4564 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4565 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4566 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4567 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4568 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4569 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4570 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4571 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4572 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4573 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4574 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4575 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4576 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4577 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4578 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4579 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4580 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4581 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4582 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4583 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4584 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4585 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4586 [CLKID_HDMI] = &g12a_hdmi.hw,
4587 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4588 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4589 [CLKID_MALI_0] = &g12a_mali_0.hw,
4590 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4591 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4592 [CLKID_MALI_1] = &g12a_mali_1.hw,
4593 [CLKID_MALI] = &g12a_mali.hw,
4594 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4595 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4596 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4597 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4598 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4599 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4600 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4601 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4602 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4603 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4604 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4605 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4606 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4607 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4608 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4609 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4610 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4611 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4612 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4613 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4614 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4615 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4616 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4617 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4618 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4619 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4620 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4621 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4622 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4623 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4624 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4625 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4626 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4627 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4628 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4629 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4630 [CLKID_TS] = &g12a_ts.hw,
4631 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
4632 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
4633 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
4634 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
4635 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
4636 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
4637 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
4638 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
4639 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
4640 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
4641 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
4642 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
4643 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
4644 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
4897 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_postmux0.hw); in meson_g12a_dvfs_setup_common()
4907 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_dyn.hw); in meson_g12a_dvfs_setup_common()
4933 notifier_clk_name = clk_hw_get_name(&g12b_cpu_clk.hw); in meson_g12b_dvfs_setup()
4942 notifier_clk_name = clk_hw_get_name(&g12b_sys1_pll.hw); in meson_g12b_dvfs_setup()
4955 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_postmux0.hw); in meson_g12b_dvfs_setup()
4965 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_dyn.hw); in meson_g12b_dvfs_setup()
4974 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk.hw); in meson_g12b_dvfs_setup()
4983 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw); in meson_g12b_dvfs_setup()
5007 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk.hw); in meson_g12a_dvfs_setup()
5016 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw); in meson_g12a_dvfs_setup()