574 	struct clk_onecell_data *clk_data;  in mtk_topckgen_init()  local
583 	clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);  in mtk_topckgen_init()
586 				    clk_data);  in mtk_topckgen_init()
589 				 clk_data);  in mtk_topckgen_init()
592 				    base, &mt7629_clk_lock, clk_data);  in mtk_topckgen_init()
594 	clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);  in mtk_topckgen_init()
595 	clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);  in mtk_topckgen_init()
596 	clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);  in mtk_topckgen_init()
598 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);  in mtk_topckgen_init()
604 	struct clk_onecell_data *clk_data;  in mtk_infrasys_init()  local
607 	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);  in mtk_infrasys_init()
610 			       clk_data);  in mtk_infrasys_init()
613 				  clk_data);  in mtk_infrasys_init()
616 				clk_data);  in mtk_infrasys_init()
625 	struct clk_onecell_data *clk_data;  in mtk_pericfg_init()  local
635 	clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);  in mtk_pericfg_init()
638 			       clk_data);  in mtk_pericfg_init()
641 				    &mt7629_clk_lock, clk_data);  in mtk_pericfg_init()
643 	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);  in mtk_pericfg_init()
647 	clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);  in mtk_pericfg_init()
654 	struct clk_onecell_data *clk_data;  in mtk_apmixedsys_init()  local
657 	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);  in mtk_apmixedsys_init()
658 	if (!clk_data)  in mtk_apmixedsys_init()
662 			      clk_data);  in mtk_apmixedsys_init()
665 			       ARRAY_SIZE(apmixed_clks), clk_data);  in mtk_apmixedsys_init()
667 	clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);  in mtk_apmixedsys_init()
668 	clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);  in mtk_apmixedsys_init()
670 	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);  in mtk_apmixedsys_init()