Lines Matching refs:clk_data

614 	struct clk_onecell_data *clk_data;  in mtk_topckgen_init()  local
623 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); in mtk_topckgen_init()
626 clk_data); in mtk_topckgen_init()
629 clk_data); in mtk_topckgen_init()
632 base, &mt7622_clk_lock, clk_data); in mtk_topckgen_init()
635 base, &mt7622_clk_lock, clk_data); in mtk_topckgen_init()
638 clk_data); in mtk_topckgen_init()
640 clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); in mtk_topckgen_init()
641 clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); in mtk_topckgen_init()
642 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); in mtk_topckgen_init()
644 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); in mtk_topckgen_init()
650 struct clk_onecell_data *clk_data; in mtk_infrasys_init() local
653 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); in mtk_infrasys_init()
656 clk_data); in mtk_infrasys_init()
659 clk_data); in mtk_infrasys_init()
662 clk_data); in mtk_infrasys_init()
673 struct clk_onecell_data *clk_data; in mtk_apmixedsys_init() local
676 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); in mtk_apmixedsys_init()
677 if (!clk_data) in mtk_apmixedsys_init()
681 clk_data); in mtk_apmixedsys_init()
684 ARRAY_SIZE(apmixed_clks), clk_data); in mtk_apmixedsys_init()
686 clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); in mtk_apmixedsys_init()
687 clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]); in mtk_apmixedsys_init()
689 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); in mtk_apmixedsys_init()
694 struct clk_onecell_data *clk_data; in mtk_pericfg_init() local
704 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); in mtk_pericfg_init()
707 clk_data); in mtk_pericfg_init()
710 &mt7622_clk_lock, clk_data); in mtk_pericfg_init()
712 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); in mtk_pericfg_init()
716 clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); in mtk_pericfg_init()