370 	u32 div_reg, div;  in ingenic_clk_recalc_rate()  local
375 		div_reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_recalc_rate()
376 		div = (div_reg >> clk_info->div.shift) &  in ingenic_clk_recalc_rate()
377 		      GENMASK(clk_info->div.bits - 1, 0);  in ingenic_clk_recalc_rate()
379 		if (clk_info->div.div_table)  in ingenic_clk_recalc_rate()
380 			div = clk_info->div.div_table[div];  in ingenic_clk_recalc_rate()
382 			div = (div + 1) * clk_info->div.div;  in ingenic_clk_recalc_rate()
384 		rate /= div;  in ingenic_clk_recalc_rate()
386 		rate /= clk_info->fixdiv.div;  in ingenic_clk_recalc_rate()
394 			unsigned int div)  in ingenic_clk_calc_hw_div()  argument
398 	for (i = 0; i < (1 << clk_info->div.bits)  in ingenic_clk_calc_hw_div()
399 				&& clk_info->div.div_table[i]; i++) {  in ingenic_clk_calc_hw_div()
400 		if (clk_info->div.div_table[i] >= div)  in ingenic_clk_calc_hw_div()
411 	unsigned int div, hw_div;  in ingenic_clk_calc_div()  local
414 	div = DIV_ROUND_UP(parent_rate, req_rate);  in ingenic_clk_calc_div()
416 	if (clk_info->div.div_table) {  in ingenic_clk_calc_div()
417 		hw_div = ingenic_clk_calc_hw_div(clk_info, div);  in ingenic_clk_calc_div()
419 		return clk_info->div.div_table[hw_div];  in ingenic_clk_calc_div()
423 	div = min_t(unsigned, div, 1 << clk_info->div.bits);  in ingenic_clk_calc_div()
424 	div = max_t(unsigned, div, 1);  in ingenic_clk_calc_div()
431 	div /= clk_info->div.div;  in ingenic_clk_calc_div()
432 	div *= clk_info->div.div;  in ingenic_clk_calc_div()
434 	return div;  in ingenic_clk_calc_div()
444 	unsigned int div = 1;  in ingenic_clk_round_rate()  local
449 		div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);  in ingenic_clk_round_rate()
451 		div = clk_info->fixdiv.div;  in ingenic_clk_round_rate()
453 	return DIV_ROUND_UP(*parent_rate, div);  in ingenic_clk_round_rate()
465 	unsigned int hw_div, div, i;  in ingenic_clk_set_rate()  local
472 		div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);  in ingenic_clk_set_rate()
473 		rate = DIV_ROUND_UP(parent_rate, div);  in ingenic_clk_set_rate()
478 		if (clk_info->div.div_table)  in ingenic_clk_set_rate()
479 			hw_div = ingenic_clk_calc_hw_div(clk_info, div);  in ingenic_clk_set_rate()
481 			hw_div = ((div / clk_info->div.div) - 1);  in ingenic_clk_set_rate()
484 		reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
487 		mask = GENMASK(clk_info->div.bits - 1, 0);  in ingenic_clk_set_rate()
488 		reg &= ~(mask << clk_info->div.shift);  in ingenic_clk_set_rate()
489 		reg |= hw_div << clk_info->div.shift;  in ingenic_clk_set_rate()
492 		if (clk_info->div.stop_bit != -1)  in ingenic_clk_set_rate()
493 			reg &= ~BIT(clk_info->div.stop_bit);  in ingenic_clk_set_rate()
496 		if (clk_info->div.ce_bit != -1)  in ingenic_clk_set_rate()
497 			reg |= BIT(clk_info->div.ce_bit);  in ingenic_clk_set_rate()
500 		writel(reg, cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
503 		if (clk_info->div.busy_bit != -1) {  in ingenic_clk_set_rate()
505 				reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
506 				if (!(reg & BIT(clk_info->div.busy_bit)))  in ingenic_clk_set_rate()