67 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \  argument
68 	imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)->clk
73 #define imx_clk_divider2(name, parent, reg, shift, width) \  argument
74 	imx_clk_hw_divider2(name, parent, reg, shift, width)->clk
76 #define imx_clk_gate_dis(name, parent, reg, shift) \  argument
77 	imx_clk_hw_gate_dis(name, parent, reg, shift)->clk
79 #define imx_clk_gate2(name, parent, reg, shift) \  argument
80 	imx_clk_hw_gate2(name, parent, reg, shift)->clk
82 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \  argument
83 	imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)->clk
85 #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \  argument
86 	imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count)->clk
88 #define imx_clk_gate3(name, parent, reg, shift) \  argument
89 	imx_clk_hw_gate3(name, parent, reg, shift)->clk
91 #define imx_clk_gate4(name, parent, reg, shift) \  argument
92 	imx_clk_hw_gate4(name, parent, reg, shift)->clk
94 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \  argument
95 	imx_clk_hw_mux(name, reg, shift, width, parents, num_parents)->clk
168 	 void __iomem *reg, u8 shift, u32 exclusive_mask);
177 				 void __iomem *reg, u8 shift, u8 width,
180 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
191 				  void __iomem *reg, u8 shift, u8 width,
195 			      u8 shift, u8 width, const char * const *parents,
209 			u8 shift, u8 width, const char * const *parents,  in imx_clk_hw_mux_ldb()  argument
214 			shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);  in imx_clk_hw_mux_ldb()
225 		void __iomem *reg, u8 shift, u8 width)  in imx_clk_divider()  argument
228 			reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_divider()
233 						void __iomem *reg, u8 shift,  in imx_clk_hw_divider()  argument
237 				       reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_hw_divider()
241 		const char *parent, void __iomem *reg, u8 shift, u8 width,  in imx_clk_divider_flags()  argument
245 			reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_divider_flags()
250 						   void __iomem *reg, u8 shift,  in imx_clk_hw_divider_flags()  argument
254 				       reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_hw_divider_flags()
258 		void __iomem *reg, u8 shift, u8 width)  in imx_clk_hw_divider2()  argument
262 			reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_hw_divider2()
266 		const char *parent, void __iomem *reg, u8 shift, u8 width,  in imx_clk_divider2_flags()  argument
271 			reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_divider2_flags()
275 		void __iomem *reg, u8 shift)  in imx_clk_gate()  argument
278 			shift, 0, &imx_ccm_lock);  in imx_clk_gate()
282 		void __iomem *reg, u8 shift, unsigned long flags)  in imx_clk_hw_gate_flags()  argument
285 			shift, 0, &imx_ccm_lock);  in imx_clk_hw_gate_flags()
289 					     void __iomem *reg, u8 shift)  in imx_clk_hw_gate()  argument
292 				    shift, 0, &imx_ccm_lock);  in imx_clk_hw_gate()
296 		void __iomem *reg, u8 shift)  in imx_clk_hw_gate_dis()  argument
299 			shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);  in imx_clk_hw_gate_dis()
303 		void __iomem *reg, u8 shift, unsigned long flags)  in imx_clk_hw_gate_dis_flags()  argument
306 			shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);  in imx_clk_hw_gate_dis_flags()
310 		void __iomem *reg, u8 shift)  in imx_clk_hw_gate2()  argument
313 			shift, 0x3, 0, &imx_ccm_lock, NULL);  in imx_clk_hw_gate2()
317 		void __iomem *reg, u8 shift, unsigned long flags)  in imx_clk_hw_gate2_flags()  argument
320 			shift, 0x3, 0, &imx_ccm_lock, NULL);  in imx_clk_hw_gate2_flags()
324 		const char *parent, void __iomem *reg, u8 shift,  in imx_clk_hw_gate2_shared()  argument
328 			shift, 0x3, 0, &imx_ccm_lock, share_count);  in imx_clk_hw_gate2_shared()
332 		const char *parent, void __iomem *reg, u8 shift,  in imx_clk_hw_gate2_shared2()  argument
336 				  CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,  in imx_clk_hw_gate2_shared2()
341 		const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)  in imx_clk_gate2_cgr()  argument
344 			shift, cgr_val, 0, &imx_ccm_lock, NULL);  in imx_clk_gate2_cgr()
348 		void __iomem *reg, u8 shift)  in imx_clk_hw_gate3()  argument
352 			reg, shift, 0, &imx_ccm_lock);  in imx_clk_hw_gate3()
356 		const char *parent, void __iomem *reg, u8 shift,  in imx_clk_gate3_flags()  argument
361 			reg, shift, 0, &imx_ccm_lock);  in imx_clk_gate3_flags()
365 		void __iomem *reg, u8 shift)  in imx_clk_hw_gate4()  argument
369 			reg, shift, 0x3, 0, &imx_ccm_lock, NULL);  in imx_clk_hw_gate4()
373 		const char *parent, void __iomem *reg, u8 shift,  in imx_clk_gate4_flags()  argument
378 			reg, shift, 0x3, 0, &imx_ccm_lock, NULL);  in imx_clk_gate4_flags()
382 			u8 shift, u8 width, const char * const *parents,  in imx_clk_hw_mux()  argument
386 			CLK_SET_RATE_NO_REPARENT, reg, shift,  in imx_clk_hw_mux()
391 			u8 shift, u8 width, const char * const *parents,  in imx_clk_mux2()  argument
396 			reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_mux2()
400 					     u8 shift, u8 width,  in imx_clk_hw_mux2()  argument
407 				   reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_hw_mux2()
411 			void __iomem *reg, u8 shift, u8 width,  in imx_clk_mux_flags()  argument
416 			flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,  in imx_clk_mux_flags()
421 		void __iomem *reg, u8 shift, u8 width,  in imx_clk_mux2_flags()  argument
427 			reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_mux2_flags()
431 						  void __iomem *reg, u8 shift,  in imx_clk_hw_mux_flags()  argument
439 				   reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_hw_mux_flags()
463 		unsigned long flags, void __iomem *reg, u8 shift, u8 width,