53 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \  argument
54 	imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk
56 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \  argument
58 	clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
61 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \  argument
62 	imx_clk_hw_pllv3(type, name, parent_name, base, div_mask)->clk
64 #define imx_clk_pfd(name, parent_name, reg, idx) \  argument
65 	imx_clk_hw_pfd(name, parent_name, reg, idx)->clk
97 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
106 struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
130 		const char *parent_name, void __iomem *base, u32 div_mask);
149 struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
153 		const char *parent_name, unsigned long flags,
170 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
173 struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
176 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
442 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
462 struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name,