627 		struct xgene_dev_parameters *parameters, spinlock_t *lock)  in xgene_register_clk()  argument
647 	apmclk->param = *parameters;  in xgene_register_clk()
672 	struct xgene_dev_parameters parameters;  in xgene_devclk_init()  local
680 	parameters.csr_reg = NULL;  in xgene_devclk_init()
681 	parameters.divider_reg = NULL;  in xgene_devclk_init()
698 			parameters.divider_reg = map_res;  in xgene_devclk_init()
700 			parameters.csr_reg = map_res;  in xgene_devclk_init()
702 	if (of_property_read_u32(np, "csr-offset", &parameters.reg_csr_offset))  in xgene_devclk_init()
703 		parameters.reg_csr_offset = 0;  in xgene_devclk_init()
704 	if (of_property_read_u32(np, "csr-mask", &parameters.reg_csr_mask))  in xgene_devclk_init()
705 		parameters.reg_csr_mask = 0xF;  in xgene_devclk_init()
707 				&parameters.reg_clk_offset))  in xgene_devclk_init()
708 		parameters.reg_clk_offset = 0x8;  in xgene_devclk_init()
709 	if (of_property_read_u32(np, "enable-mask", &parameters.reg_clk_mask))  in xgene_devclk_init()
710 		parameters.reg_clk_mask = 0xF;  in xgene_devclk_init()
712 				&parameters.reg_divider_offset))  in xgene_devclk_init()
713 		parameters.reg_divider_offset = 0;  in xgene_devclk_init()
715 				&parameters.reg_divider_width))  in xgene_devclk_init()
716 		parameters.reg_divider_width = 0;  in xgene_devclk_init()
718 				&parameters.reg_divider_shift))  in xgene_devclk_init()
719 		parameters.reg_divider_shift = 0;  in xgene_devclk_init()
723 		of_clk_get_parent_name(np, 0), &parameters, &clk_lock);  in xgene_devclk_init()
734 	if (parameters.csr_reg)  in xgene_devclk_init()
735 		iounmap(parameters.csr_reg);  in xgene_devclk_init()
736 	if (parameters.divider_reg)  in xgene_devclk_init()
737 		iounmap(parameters.divider_reg);  in xgene_devclk_init()