Lines Matching refs:PLL_DIV3
24 #define PLL_DIV3 2 macro
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
255 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
264 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
268 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
277 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
281 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
290 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
294 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
303 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
307 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
316 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
325 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
329 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
338 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
358 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
373 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
377 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
386 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
390 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
399 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
403 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
410 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
420 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
424 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },