27 #define PLATFORM_PLL	0  macro
248 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
261 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
274 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
287 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
327 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
375 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
388 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
396 		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
412 		[5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
422 		[5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
441 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p2041_init_periph()
453 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
458 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p4080_init_periph()
473 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5020_init_periph()
488 		cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()
493 		cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;  in p5040_init_periph()
503 	cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;  in t1040_init_periph()
943 	plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);  in create_one_cmux()
1152 	if (cg->coreclk && idx != PLATFORM_PLL) {  in create_one_pll()
1161 		case PLATFORM_PLL:  in create_one_pll()
1181 		if (idx == PLATFORM_PLL)  in create_one_pll()
1197 	    ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))  in create_one_pll()
1210 		if (idx != PLATFORM_PLL && i >= 4)  in create_one_pll()
1293 	legacy_pll_init(np, PLATFORM_PLL);  in pltfrm_pll_init()
1354 		pll = &cg->pll[PLATFORM_PLL];  in clockgen_clk_get()