Lines Matching refs:CGA_PLL2
29 #define CGA_PLL2 2 macro
123 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
130 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
131 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
139 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
146 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
147 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
155 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
156 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
164 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
165 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
173 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
174 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
200 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
201 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
212 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
213 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
214 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
228 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
229 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
230 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
254 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
255 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
262 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
263 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
264 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
265 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
280 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
281 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
288 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
289 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
290 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
291 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
306 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
307 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
314 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
316 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
328 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
329 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
336 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
337 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
338 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
376 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
377 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
384 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
385 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
386 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
387 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
402 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
403 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
439 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
471 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; in p5020_init_periph()
1167 case CGA_PLL2: in create_one_pll()