Lines Matching full:width
45 u8 width) in _get_table_maxdiv() argument
47 unsigned int maxdiv = 0, mask = clk_div_mask(width); in _get_table_maxdiv()
67 static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width, in _get_maxdiv() argument
71 return clk_div_mask(width); in _get_maxdiv()
73 return 1 << clk_div_mask(width); in _get_maxdiv()
75 return _get_table_maxdiv(table, width); in _get_maxdiv()
76 return clk_div_mask(width) + 1; in _get_maxdiv()
91 unsigned int val, unsigned long flags, u8 width) in _get_div() argument
98 return val ? val : clk_div_mask(width) + 1; in _get_div()
116 unsigned int div, unsigned long flags, u8 width) in _get_val() argument
123 return (div == clk_div_mask(width) + 1) ? 0 : div; in _get_val()
132 unsigned long flags, unsigned long width) in divider_recalc_rate() argument
136 div = _get_div(table, val, flags, width); in divider_recalc_rate()
155 val &= clk_div_mask(divider->width); in clk_divider_recalc_rate()
158 divider->flags, divider->width); in clk_divider_recalc_rate()
291 const struct clk_div_table *table, u8 width, in clk_divider_bestdiv() argument
301 maxdiv = _get_maxdiv(table, width, flags); in clk_divider_bestdiv()
338 bestdiv = _get_maxdiv(table, width, flags); in clk_divider_bestdiv()
348 u8 width, unsigned long flags) in divider_round_rate_parent() argument
352 div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags); in divider_round_rate_parent()
360 const struct clk_div_table *table, u8 width, in divider_ro_round_rate_parent() argument
365 div = _get_div(table, val, flags, width); in divider_ro_round_rate_parent()
390 val &= clk_div_mask(divider->width); in clk_divider_round_rate()
393 divider->width, divider->flags, in clk_divider_round_rate()
398 divider->width, divider->flags); in clk_divider_round_rate()
402 const struct clk_div_table *table, u8 width, in divider_get_val() argument
412 value = _get_val(table, div, flags, width); in divider_get_val()
414 return min_t(unsigned int, value, clk_div_mask(width)); in divider_get_val()
427 divider->width, divider->flags); in clk_divider_set_rate()
437 val = clk_div_mask(divider->width) << (divider->shift + 16); in clk_divider_set_rate()
440 val &= ~(clk_div_mask(divider->width) << divider->shift); in clk_divider_set_rate()
468 void __iomem *reg, u8 shift, u8 width, in _register_divider() argument
478 if (width + shift > 16) { in _register_divider()
501 div->width = width; in _register_divider()
526 * @width: width of the bitfield
532 void __iomem *reg, u8 shift, u8 width, in clk_register_divider() argument
538 width, clk_divider_flags, NULL, lock); in clk_register_divider()
553 * @width: width of the bitfield
559 void __iomem *reg, u8 shift, u8 width, in clk_hw_register_divider() argument
563 width, clk_divider_flags, NULL, lock); in clk_hw_register_divider()
576 * @width: width of the bitfield
583 void __iomem *reg, u8 shift, u8 width, in clk_register_divider_table() argument
590 width, clk_divider_flags, table, lock); in clk_register_divider_table()
606 * @width: width of the bitfield
613 void __iomem *reg, u8 shift, u8 width, in clk_hw_register_divider_table() argument
618 width, clk_divider_flags, table, lock); in clk_hw_register_divider_table()