Lines Matching refs:TLCLK_REG0
136 #define TLCLK_REG0 TLCLK_BASE macro
516 SET_PORT_BITS(TLCLK_REG0, 0xfc, 2); in store_select_amcb2_transmit_clock()
519 SET_PORT_BITS(TLCLK_REG0, 0xfc, 0); in store_select_amcb2_transmit_clock()
522 SET_PORT_BITS(TLCLK_REG0, 0xfc, 3); in store_select_amcb2_transmit_clock()
525 SET_PORT_BITS(TLCLK_REG0, 0xfc, 1); in store_select_amcb2_transmit_clock()
558 SET_PORT_BITS(TLCLK_REG0, 0xfc, 2); in store_select_amcb1_transmit_clock()
561 SET_PORT_BITS(TLCLK_REG0, 0xfc, 0); in store_select_amcb1_transmit_clock()
564 SET_PORT_BITS(TLCLK_REG0, 0xfc, 3); in store_select_amcb1_transmit_clock()
567 SET_PORT_BITS(TLCLK_REG0, 0xfc, 1); in store_select_amcb1_transmit_clock()
635 SET_PORT_BITS(TLCLK_REG0, 0xfb, val); in store_filter_select()
655 SET_PORT_BITS(TLCLK_REG0, 0xbf, val); in store_hardware_switching_mode()
676 SET_PORT_BITS(TLCLK_REG0, 0x7f, val); in store_hardware_switching()
694 SET_PORT_BITS(TLCLK_REG0, 0xf7, 0); in store_refalign()
695 SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08); in store_refalign()
696 SET_PORT_BITS(TLCLK_REG0, 0xf7, 0); in store_refalign()
716 SET_PORT_BITS(TLCLK_REG0, 0xcf, val); in store_mode_select()