493 	readl(dimm_mmio);	/* MMIO PCI posting flush */  in pdc20621_dma_prep()
528 	readl(dimm_mmio);	/* MMIO PCI posting flush */  in pdc20621_nodata_prep()
559 	readl(mmio + PDC_20621_SEQCTL + (seq * 4));	/* flush */  in __pdc20621_push_hdma()
562 	readl(mmio + PDC_HDMA_PKT_SUBMIT);	/* flush */  in __pdc20621_push_hdma()
612 	printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));  in pdc20621_dump_hdma()
613 	printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));  in pdc20621_dump_hdma()
614 	printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));  in pdc20621_dump_hdma()
615 	printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));  in pdc20621_dump_hdma()
652 		readl(mmio + PDC_20621_SEQCTL + (seq * 4));	/* flush */  in pdc20621_packet_start()
656 		readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);  in pdc20621_packet_start()
705 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
716 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
731 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
735 			readl(mmio + PDC_20621_SEQCTL + (seq * 4));  in pdc20621_host_intr()
738 			readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);  in pdc20621_host_intr()
744 				readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));  in pdc20621_host_intr()
793 	mask = readl(mmio_base + PDC_20621_SEQMASK);  in pdc20621_interrupt()
844 	tmp = readl(mmio + PDC_CTLSTAT);  in pdc_freeze()
848 	readl(mmio + PDC_CTLSTAT); /* flush */  in pdc_freeze()
862 	tmp = readl(mmio + PDC_CTLSTAT);  in pdc_thaw()
865 	readl(mmio + PDC_CTLSTAT); /* flush */  in pdc_thaw()
877 		tmp = readl(mmio);  in pdc_reset_port()
889 	readl(mmio);	/* flush */  in pdc_reset_port()
999 	readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1001 	readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1013 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1015 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1024 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1026 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1051 	readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1058 	readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1064 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1067 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1075 		readl(mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1078 		readl(mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1099 	readl(mmio + PDC_I2C_ADDR_DATA);  in pdc20621_i2c_read()
1106 		status = readl(mmio + PDC_I2C_CONTROL);  in pdc20621_i2c_read()
1108 			status = readl(mmio + PDC_I2C_ADDR_DATA);  in pdc20621_i2c_read()
1199 	readl(mmio + PDC_DIMM0_CONTROL);  in pdc20621_prog_dimm0()
1222 	readl(mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1234 		readl(mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1245 		data = readl(mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1274 	time_period = readl(mmio + PDC_TIME_PERIOD);  in pdc20621_dimm_init()
1279 	readl(mmio + PDC_TIME_CONTROL);  in pdc20621_dimm_init()
1289 	tcount = readl(mmio + PDC_TIME_COUNTER);  in pdc20621_dimm_init()
1318 	readl(mmio + PDC_CTL_STATUS);  in pdc20621_dimm_init()
1408 	tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;  in pdc_20621_init()
1415 	tmp = readl(mmio + PDC_HDMA_CTLSTAT);  in pdc_20621_init()
1418 	readl(mmio + PDC_HDMA_CTLSTAT);		/* flush */  in pdc_20621_init()
1422 	tmp = readl(mmio + PDC_HDMA_CTLSTAT);  in pdc_20621_init()
1425 	readl(mmio + PDC_HDMA_CTLSTAT);		/* flush */  in pdc_20621_init()