4017 	return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);  in is_shadow_zero_bits_set()
4651 	struct rsvd_bits_validate *shadow_zero_check;  in reset_shadow_zero_bits_mask()  local
4658 	shadow_zero_check = &context->shadow_zero_check;  in reset_shadow_zero_bits_mask()
4659 	__reset_rsvds_bits_mask(vcpu, shadow_zero_check,  in reset_shadow_zero_bits_mask()
4669 		shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;  in reset_shadow_zero_bits_mask()
4670 		shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;  in reset_shadow_zero_bits_mask()
4690 	struct rsvd_bits_validate *shadow_zero_check;  in reset_tdp_shadow_zero_bits_mask()  local
4693 	shadow_zero_check = &context->shadow_zero_check;  in reset_tdp_shadow_zero_bits_mask()
4696 		__reset_rsvds_bits_mask(vcpu, shadow_zero_check,  in reset_tdp_shadow_zero_bits_mask()
4702 		__reset_rsvds_bits_mask_ept(shadow_zero_check,  in reset_tdp_shadow_zero_bits_mask()
4710 		shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;  in reset_tdp_shadow_zero_bits_mask()
4711 		shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;  in reset_tdp_shadow_zero_bits_mask()
4723 	__reset_rsvds_bits_mask_ept(&context->shadow_zero_check,  in reset_ept_shadow_zero_bits_mask()