119 static enum smca_bank_types smca_get_bank_type(unsigned int bank)  in smca_get_bank_type()  argument
123 	if (bank >= MAX_NR_BANKS)  in smca_get_bank_type()
126 	b = &smca_banks[bank];  in smca_get_bank_type()
207 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu)  in smca_set_misc_banks_map()  argument
215 	if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))  in smca_set_misc_banks_map()
221 	if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high))  in smca_set_misc_banks_map()
225 		per_cpu(smca_misc_banks_map, cpu) |= BIT(bank);  in smca_set_misc_banks_map()
229 static void smca_configure(unsigned int bank, unsigned int cpu)  in smca_configure()  argument
234 	u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);  in smca_configure()
266 	smca_set_misc_banks_map(bank, cpu);  in smca_configure()
269 	if (smca_banks[bank].hwid)  in smca_configure()
272 	if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {  in smca_configure()
273 		pr_warn("Failed to read MCA_IPID for bank %d\n", bank);  in smca_configure()
283 			smca_banks[bank].hwid = s_hwid;  in smca_configure()
284 			smca_banks[bank].id = low;  in smca_configure()
285 			smca_banks[bank].sysfs_id = s_hwid->count++;  in smca_configure()
299 static inline bool is_shared_bank(int bank)  in is_shared_bank()  argument
309 	return (bank == 4);  in is_shared_bank()
332 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)  in lvt_interrupt_supported()  argument
337 	if (bank == 4)  in lvt_interrupt_supported()
354 		       b->bank, b->block, b->address, hi, lo);  in lvt_off_valid()
369 		       b->cpu, apic, b->bank, b->block, b->address, hi, lo);  in lvt_off_valid()
478 static u32 smca_get_block_address(unsigned int bank, unsigned int block,  in smca_get_block_address()  argument
482 		return MSR_AMD64_SMCA_MCx_MISC(bank);  in smca_get_block_address()
484 	if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank)))  in smca_get_block_address()
487 	return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);  in smca_get_block_address()
491 			     unsigned int bank, unsigned int block,  in get_block_address()  argument
496 	if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))  in get_block_address()
500 		return smca_get_block_address(bank, block, cpu);  in get_block_address()
505 		addr = msr_ops.misc(bank);  in get_block_address()
519 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,  in prepare_threshold_block()  argument
528 		per_cpu(bank_map, cpu) |= (1 << bank);  in prepare_threshold_block()
532 	b.bank			= bank;  in prepare_threshold_block()
535 	b.interrupt_capable	= lvt_interrupt_supported(bank, misc_high);  in prepare_threshold_block()
567 	enum smca_bank_types bank_type = smca_get_bank_type(m->bank);  in amd_filter_mce()
586 void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)  in disable_err_thresholding()  argument
593 	if (c->x86 == 0x15 && bank == 4) {  in disable_err_thresholding()
600 		if (smca_get_bank_type(bank) != SMCA_IF)  in disable_err_thresholding()
603 		msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);  in disable_err_thresholding()
628 	unsigned int bank, block, cpu = smp_processor_id();  in mce_amd_feature_init()  local
633 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {  in mce_amd_feature_init()
635 			smca_configure(bank, cpu);  in mce_amd_feature_init()
637 		disable_err_thresholding(c, bank);  in mce_amd_feature_init()
640 			address = get_block_address(address, low, high, bank, block, cpu);  in mce_amd_feature_init()
654 			offset = prepare_threshold_block(bank, block, address, offset, high);  in mce_amd_feature_init()
868 		return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0;  in amd_mce_is_memory_error()
870 	return m->bank == 4 && xec == 0x8;  in amd_mce_is_memory_error()
873 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)  in __log_error()  argument
881 	m.bank   = bank;  in __log_error()
899 		rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);  in __log_error()
902 			rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);  in __log_error()
922 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)  in _log_error_bank()  argument
933 	__log_error(bank, status, addr, misc);  in _log_error_bank()
949 static void log_error_deferred(unsigned int bank)  in log_error_deferred()  argument
953 	defrd = _log_error_bank(bank, msr_ops.status(bank),  in log_error_deferred()
954 					msr_ops.addr(bank), 0);  in log_error_deferred()
961 		wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);  in log_error_deferred()
969 	_log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),  in log_error_deferred()
970 			      MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);  in log_error_deferred()
976 	unsigned int bank;  in amd_deferred_error_interrupt()  local
978 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank)  in amd_deferred_error_interrupt()
979 		log_error_deferred(bank);  in amd_deferred_error_interrupt()
982 static void log_error_thresholding(unsigned int bank, u64 misc)  in log_error_thresholding()  argument
984 	_log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc);  in log_error_thresholding()
1002 	log_error_thresholding(block->bank, ((u64)high << 32) | low);  in log_and_reset_block()
1017 	unsigned int bank, cpu = smp_processor_id();  in amd_threshold_interrupt()  local
1019 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {  in amd_threshold_interrupt()
1020 		if (!(per_cpu(bank_map, cpu) & (1 << bank)))  in amd_threshold_interrupt()
1023 		first_block = per_cpu(threshold_banks, cpu)[bank]->blocks;  in amd_threshold_interrupt()
1169 static const char *get_name(unsigned int bank, struct threshold_block *b)  in get_name()  argument
1174 		if (b && bank == 4)  in get_name()
1177 		return th_names[bank];  in get_name()
1180 	bank_type = smca_get_bank_type(bank);  in get_name()
1190 	if (smca_banks[bank].hwid->count == 1)  in get_name()
1195 			  smca_banks[bank].sysfs_id);  in get_name()
1199 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,  in allocate_threshold_blocks()  argument
1206 	if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))  in allocate_threshold_blocks()
1228 	b->bank			= bank;  in allocate_threshold_blocks()
1232 	b->interrupt_capable	= lvt_interrupt_supported(bank, high);  in allocate_threshold_blocks()
1244 	if (per_cpu(threshold_banks, cpu)[bank]->blocks) {  in allocate_threshold_blocks()
1246 			 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);  in allocate_threshold_blocks()
1248 		per_cpu(threshold_banks, cpu)[bank]->blocks = b;  in allocate_threshold_blocks()
1252 				   per_cpu(threshold_banks, cpu)[bank]->kobj,  in allocate_threshold_blocks()
1253 				   get_name(bank, b));  in allocate_threshold_blocks()
1257 	address = get_block_address(address, low, high, bank, ++block, cpu);  in allocate_threshold_blocks()
1261 	err = allocate_threshold_blocks(cpu, bank, block, address);  in allocate_threshold_blocks()
1303 static int threshold_create_bank(unsigned int cpu, unsigned int bank)  in threshold_create_bank()  argument
1308 	const char *name = get_name(bank, NULL);  in threshold_create_bank()
1314 	if (is_shared_bank(bank)) {  in threshold_create_bank()
1325 			per_cpu(threshold_banks, cpu)[bank] = b;  in threshold_create_bank()
1346 	per_cpu(threshold_banks, cpu)[bank] = b;  in threshold_create_bank()
1348 	if (is_shared_bank(bank)) {  in threshold_create_bank()
1358 	err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank));  in threshold_create_bank()
1370 						 unsigned int bank)  in deallocate_threshold_block()  argument
1374 	struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];  in deallocate_threshold_block()
1385 	kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);  in deallocate_threshold_block()
1386 	per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;  in deallocate_threshold_block()
1400 static void threshold_remove_bank(unsigned int cpu, int bank)  in threshold_remove_bank()  argument
1405 	b = per_cpu(threshold_banks, cpu)[bank];  in threshold_remove_bank()
1412 	if (is_shared_bank(bank)) {  in threshold_remove_bank()
1415 			per_cpu(threshold_banks, cpu)[bank] = NULL;  in threshold_remove_bank()
1427 	deallocate_threshold_block(cpu, bank);  in threshold_remove_bank()
1433 	per_cpu(threshold_banks, cpu)[bank] = NULL;  in threshold_remove_bank()
1438 	unsigned int bank;  in mce_threshold_remove_device()  local
1440 	for (bank = 0; bank < per_cpu(mce_num_banks, cpu); ++bank) {  in mce_threshold_remove_device()
1441 		if (!(per_cpu(bank_map, cpu) & (1 << bank)))  in mce_threshold_remove_device()
1443 		threshold_remove_bank(cpu, bank);  in mce_threshold_remove_device()
1453 	unsigned int bank;  in mce_threshold_create_device()  local
1468 	for (bank = 0; bank < per_cpu(mce_num_banks, cpu); ++bank) {  in mce_threshold_create_device()
1469 		if (!(per_cpu(bank_map, cpu) & (1 << bank)))  in mce_threshold_create_device()
1471 		err = threshold_create_bank(cpu, bank);  in mce_threshold_create_device()