Lines Matching defs:cpu_hw_events

186 struct cpu_hw_events {  struct
190 	struct perf_event	*events[X86_PMC_IDX_MAX]; /* in counter order */
191 	unsigned long		active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
192 	unsigned long		running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
193 	int			enabled;
195 	int			n_events; /* the # of events in the below arrays */
196 	int			n_added;  /* the # last events in the below arrays;
198 	int			n_txn;    /* the # last events in the below arrays;
200 	int			assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
201 	u64			tags[X86_PMC_IDX_MAX];
203 	struct perf_event	*event_list[X86_PMC_IDX_MAX]; /* in enabled order */
204 	struct event_constraint	*event_constraint[X86_PMC_IDX_MAX];
206 	int			n_excl; /* the number of exclusive events */
208 	unsigned int		txn_flags;
209 	int			is_fake;
214 	struct debug_store	*ds;
215 	void			*ds_pebs_vaddr;
216 	void			*ds_bts_vaddr;
217 	u64			pebs_enabled;
218 	int			n_pebs;
219 	int			n_large_pebs;
220 	int			n_pebs_via_pt;
221 	int			pebs_output;
224 	u64			pebs_data_cfg;
225 	u64			active_pebs_data_cfg;
226 	int			pebs_record_size;
231 	int				lbr_users;
232 	int				lbr_pebs_users;
233 	struct perf_branch_stack	lbr_stack;
234 	struct perf_branch_entry	lbr_entries[MAX_LBR_ENTRIES];
235 	struct er_account		*lbr_sel;
236 	u64				br_sel;
237 	struct x86_perf_task_context	*last_task_ctx;
238 	int				last_log_id;
243 	u64				intel_ctrl_guest_mask;
244 	u64				intel_ctrl_host_mask;
245 	struct perf_guest_switch_msr	guest_switch_msrs[X86_PMC_IDX_MAX];
250 	u64				intel_cp_status;
256 	struct intel_shared_regs	*shared_regs;
260 	struct event_constraint *constraint_list; /* in enable order */
261 	struct intel_excl_cntrs		*excl_cntrs;
262 	int excl_thread_id; /* 0 or 1 */
267 	u64				tfa_shadow;
272 	struct amd_nb			*amd_nb;
274 	u64				perf_ctr_virt_mask;
276 	void				*kfree_on_online[X86_PERF_KFREE_MAX];