Lines Matching refs:x86_pmu
180 if (x86_pmu.pebs_no_tlb) { in load_latency_data()
338 size_t bsiz = x86_pmu.pebs_buffer_size; in alloc_pebs_buffer()
342 if (!x86_pmu.pebs) in alloc_pebs_buffer()
353 if (x86_pmu.intel_cap.pebs_format < 2) { in alloc_pebs_buffer()
367 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size); in alloc_pebs_buffer()
377 if (!x86_pmu.pebs) in release_pebs_buffer()
385 ds_clear_cea(cea, x86_pmu.pebs_buffer_size); in release_pebs_buffer()
386 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); in release_pebs_buffer()
397 if (!x86_pmu.bts) in alloc_bts_buffer()
424 if (!x86_pmu.bts) in release_bts_buffer()
452 if (!x86_pmu.bts && !x86_pmu.pebs) in release_ds_buffers()
478 x86_pmu.bts_active = 0; in reserve_ds_buffers()
479 x86_pmu.pebs_active = 0; in reserve_ds_buffers()
481 if (!x86_pmu.bts && !x86_pmu.pebs) in reserve_ds_buffers()
484 if (!x86_pmu.bts) in reserve_ds_buffers()
487 if (!x86_pmu.pebs) in reserve_ds_buffers()
520 if (x86_pmu.bts && !bts_err) in reserve_ds_buffers()
521 x86_pmu.bts_active = 1; in reserve_ds_buffers()
523 if (x86_pmu.pebs && !pebs_err) in reserve_ds_buffers()
524 x86_pmu.pebs_active = 1; in reserve_ds_buffers()
600 if (!x86_pmu.bts_active) in intel_pmu_drain_bts_buffer()
674 x86_pmu.drain_pebs(®s); in intel_pmu_drain_pebs_buffer()
879 if (x86_pmu.pebs_constraints) { in intel_pebs_constraints()
880 for_each_event_constraint(c, x86_pmu.pebs_constraints) { in intel_pebs_constraints()
892 if (x86_pmu.flags & PMU_FL_PEBS_ALL) in intel_pebs_constraints()
928 if (x86_pmu.flags & PMU_FL_PEBS_ALL) in pebs_update_threshold()
929 reserved = x86_pmu.max_pebs_events + x86_pmu.num_counters_fixed; in pebs_update_threshold()
931 reserved = x86_pmu.max_pebs_events; in pebs_update_threshold()
956 sz += x86_pmu.lbr_nr * sizeof(struct pebs_lbr_entry); in adaptive_pebs_record_size_update()
990 x86_pmu.rtm_abort_event); in pebs_update_adaptive_cfg()
1005 ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT); in pebs_update_adaptive_cfg()
1036 if (x86_pmu.intel_cap.pebs_baseline && add) { in pebs_update_state()
1112 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5)) in intel_pmu_pebs_enable()
1117 if (x86_pmu.intel_cap.pebs_baseline) { in intel_pmu_pebs_enable()
1135 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; in intel_pmu_pebs_enable()
1170 (x86_pmu.version < 5)) in intel_pmu_pebs_disable()
1212 if (!x86_pmu.intel_cap.pebs_trap) in intel_pmu_pebs_fixup_ip()
1314 if (x86_pmu.intel_cap.pebs_format < 4) in get_pebs_status()
1429 if (x86_pmu.intel_cap.pebs_format >= 2) { in setup_pebs_fixed_sample_data()
1454 x86_pmu.intel_cap.pebs_format >= 1) in setup_pebs_fixed_sample_data()
1457 if (x86_pmu.intel_cap.pebs_format >= 2) { in setup_pebs_fixed_sample_data()
1473 if (x86_pmu.intel_cap.pebs_format >= 3 && in setup_pebs_fixed_sample_data()
1626 if (x86_pmu.intel_cap.pebs_format < 1) in get_next_pebs_record_by_bit()
1637 if (x86_pmu.intel_cap.pebs_format >= 3) in get_next_pebs_record_by_bit()
1669 int shift = 64 - x86_pmu.cntval_bits; in intel_pmu_save_and_restart_reload()
1778 if (!x86_pmu.pebs_active) in intel_pmu_drain_pebs_core()
1838 if (!x86_pmu.pebs_active) in intel_pmu_drain_pebs_nhm()
1846 mask = (1ULL << x86_pmu.max_pebs_events) - 1; in intel_pmu_drain_pebs_nhm()
1847 size = x86_pmu.max_pebs_events; in intel_pmu_drain_pebs_nhm()
1848 if (x86_pmu.flags & PMU_FL_PEBS_ALL) { in intel_pmu_drain_pebs_nhm()
1849 mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED; in intel_pmu_drain_pebs_nhm()
1850 size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed; in intel_pmu_drain_pebs_nhm()
1858 for (at = base; at < top; at += x86_pmu.pebs_record_size) { in intel_pmu_drain_pebs_nhm()
1866 if (x86_pmu.intel_cap.pebs_format >= 3) { in intel_pmu_drain_pebs_nhm()
1886 x86_pmu.max_pebs_events); in intel_pmu_drain_pebs_nhm()
1887 if (bit >= x86_pmu.max_pebs_events) in intel_pmu_drain_pebs_nhm()
1951 if (!x86_pmu.pebs_active) in intel_pmu_drain_pebs_icl()
1959 mask = ((1ULL << x86_pmu.max_pebs_events) - 1) | in intel_pmu_drain_pebs_icl()
1960 (((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED); in intel_pmu_drain_pebs_icl()
1961 size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed; in intel_pmu_drain_pebs_icl()
2007 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); in intel_ds_init()
2008 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); in intel_ds_init()
2009 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE; in intel_ds_init()
2010 if (x86_pmu.version <= 4) in intel_ds_init()
2011 x86_pmu.pebs_no_isolation = 1; in intel_ds_init()
2013 if (x86_pmu.pebs) { in intel_ds_init()
2014 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; in intel_ds_init()
2016 int format = x86_pmu.intel_cap.pebs_format; in intel_ds_init()
2019 x86_pmu.intel_cap.pebs_baseline = 0; in intel_ds_init()
2024 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); in intel_ds_init()
2032 x86_pmu.pebs_buffer_size = PAGE_SIZE; in intel_ds_init()
2033 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; in intel_ds_init()
2038 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); in intel_ds_init()
2039 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; in intel_ds_init()
2044 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw); in intel_ds_init()
2045 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; in intel_ds_init()
2050 x86_pmu.pebs_record_size = in intel_ds_init()
2052 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; in intel_ds_init()
2053 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; in intel_ds_init()
2057 x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl; in intel_ds_init()
2058 x86_pmu.pebs_record_size = sizeof(struct pebs_basic); in intel_ds_init()
2059 if (x86_pmu.intel_cap.pebs_baseline) { in intel_ds_init()
2060 x86_pmu.large_pebs_flags |= in intel_ds_init()
2063 x86_pmu.flags |= PMU_FL_PEBS_ALL; in intel_ds_init()
2068 x86_pmu.large_pebs_flags &= in intel_ds_init()
2078 if (x86_pmu.intel_cap.pebs_output_pt_available) { in intel_ds_init()
2087 x86_pmu.pebs = 0; in intel_ds_init()
2096 if (!x86_pmu.bts && !x86_pmu.pebs) in perf_restore_debug_store()