Lines Matching full:bits
50 #define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */
51 #define PCI_SIZE_0 0x44 /* 32 bits */
52 #define PCI_SIZE_1 0x48 /* 32 bits */
53 #define PCI_SIZE_2 0x4c /* 32 bits */
54 #define PCI_SIZE_3 0x50 /* 32 bits */
55 #define PCI_SIZE_4 0x54 /* 32 bits */
56 #define PCI_SIZE_5 0x58 /* 32 bits */
57 #define PCI_PIO_CONTROL 0x60 /* 8 bits */
58 #define PCI_DVMA_CONTROL 0x62 /* 8 bits */
63 #define PCI_INTERRUPT_CONTROL 0x63 /* 8 bits */
64 #define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */
65 #define PCI_DIAGNOSTIC_1 0x68 /* 16 bits */
66 #define PCI_SOFTWARE_INT_CLEAR 0x6a /* 16 bits */
67 #define PCI_SOFTWARE_INT_SET 0x6e /* 16 bits */
68 #define PCI_SYS_INT_PENDING 0x70 /* 32 bits */
73 #define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */
74 #define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */
75 #define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */
76 #define PCI_SYS_INT_PENDING_CLEAR 0x83 /* 8 bits */
81 #define PCI_IOTLB_CONTROL 0x84 /* 8 bits */
82 #define PCI_INT_SELECT_LO 0x88 /* 16 bits */
83 #define PCI_ARBITRATION_SELECT 0x8a /* 16 bits */
84 #define PCI_INT_SELECT_HI 0x8c /* 16 bits */
85 #define PCI_HW_INT_OUTPUT 0x8e /* 16 bits */
86 #define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */
87 #define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */
88 #define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */
89 #define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */
90 #define PCI_SMBAR0 0xa0 /* 8 bits */
91 #define PCI_MSIZE0 0xa1 /* 8 bits */
92 #define PCI_PMBAR0 0xa2 /* 8 bits */
93 #define PCI_SMBAR1 0xa4 /* 8 bits */
94 #define PCI_MSIZE1 0xa5 /* 8 bits */
95 #define PCI_PMBAR1 0xa6 /* 8 bits */
96 #define PCI_SIBAR 0xa8 /* 8 bits */
98 #define PCI_ISIZE 0xa9 /* 8 bits */
104 #define PCI_PIBAR 0xaa /* 8 bits */
105 #define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */
106 #define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */
107 #define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */
108 #define PCI_SYS_LIMIT 0xb8 /* 32 bits */
109 #define PCI_SYS_COUNTER 0xbc /* 32 bits */
111 #define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */
112 #define PCI_USER_TIMER_CONTROL 0xc4 /* 8 bits */
113 #define PCI_USER_TIMER_CONFIG 0xc5 /* 8 bits */
114 #define PCI_COUNTER_IRQ 0xc6 /* 8 bits */
119 #define PCI_PIO_ERROR_COMMAND 0xc7 /* 8 bits */
120 #define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */
121 #define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */
122 #define PCI_SYS_STATUS 0xd0 /* 8 bits */