Lines Matching refs:srcreg
245 int srcreg; in misaligned_store() local
253 srcreg = (opcode >> 4) & 0x3f; in misaligned_store()
263 *(__u16 *) &buffer = (__u16) regs->regs[srcreg]; in misaligned_store()
266 *(__u32 *) &buffer = (__u32) regs->regs[srcreg]; in misaligned_store()
269 buffer = regs->regs[srcreg]; in misaligned_store()
282 __u64 val = regs->regs[srcreg]; in misaligned_store()
389 int srcreg; in misaligned_fpu_store() local
397 srcreg = (opcode >> 4) & 0x3f; in misaligned_fpu_store()
420 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
424 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
425 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1]; in misaligned_fpu_store()
428 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
429 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg+1]; in misaligned_fpu_store()
431 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg]; in misaligned_fpu_store()
432 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1]; in misaligned_fpu_store()