Lines Matching refs:r5
24 basr %r5,0
25 0: al %r5,21f-0b(%r5) /* get &_vdso_data */
36 1: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
41 s %r0,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */
42 sl %r1,__VDSO_XTIME_STAMP+4(%r5)
45 2: ms %r0,__VDSO_TK_MULT(%r5) /* * tk->mult */
47 l %r0,__VDSO_TK_MULT(%r5)
51 a %r0,__VDSO_TK_MULT(%r5)
53 al %r0,__VDSO_WTOM_NSEC(%r5)
54 al %r1,__VDSO_WTOM_NSEC+4(%r5)
57 5: l %r2,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */
59 l %r2,__VDSO_WTOM_SEC+4(%r5)
60 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
62 basr %r5,0
65 cl %r1,20f-6b(%r5)
68 sl %r1,20f-6b(%r5)
83 9: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
86 l %r2,__VDSO_WTOM_CRS_SEC+4(%r5)
87 l %r1,__VDSO_WTOM_CRS_NSEC+4(%r5)
88 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
93 10: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
96 l %r2,__VDSO_XTIME_CRS_SEC+4(%r5)
97 l %r1,__VDSO_XTIME_CRS_NSEC+4(%r5)
98 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
103 11: l %r4,__VDSO_UPD_COUNT+4(%r5) /* load update counter */
107 lm %r0,%r1,__VDSO_TS_END(%r5) /* TOD steering end time */
115 tm __VDSO_TS_DIR+3(%r5),0x01 /* steering direction? */
127 25: s %r0,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */
128 sl %r1,__VDSO_XTIME_STAMP+4(%r5)
131 12: ms %r0,__VDSO_TK_MULT(%r5) /* * tk->mult */
133 l %r0,__VDSO_TK_MULT(%r5)
137 a %r0,__VDSO_TK_MULT(%r5)
139 al %r0,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */
140 al %r1,__VDSO_XTIME_NSEC+4(%r5)
143 14: l %r2,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */
145 l %r2,__VDSO_XTIME_SEC+4(%r5)
146 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
148 basr %r5,0
151 cl %r1,20f-15b(%r5)
154 sl %r1,20f-15b(%r5)