Lines Matching refs:RISCV_OP_UNSUPP

45 	[PERF_COUNT_HW_CACHE_REFERENCES]	= RISCV_OP_UNSUPP,
46 	[PERF_COUNT_HW_CACHE_MISSES]		= RISCV_OP_UNSUPP,
47 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= RISCV_OP_UNSUPP,
48 	[PERF_COUNT_HW_BRANCH_MISSES]		= RISCV_OP_UNSUPP,
49 	[PERF_COUNT_HW_BUS_CYCLES]		= RISCV_OP_UNSUPP,
58 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
59 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
62 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
63 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
66 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
67 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
72 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
73 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
76 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
77 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
80 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
81 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
86 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
87 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
90 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
91 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
94 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
95 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
100 			[C(RESULT_ACCESS)] =  RISCV_OP_UNSUPP,
101 			[C(RESULT_MISS)] =  RISCV_OP_UNSUPP,
104 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
105 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
108 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
109 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
114 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
115 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
118 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
119 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
122 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
123 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
128 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
129 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
132 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
133 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
136 			[C(RESULT_ACCESS)] = RISCV_OP_UNSUPP,
137 			[C(RESULT_MISS)] = RISCV_OP_UNSUPP,
172 	if (code == RISCV_OP_UNSUPP)  in riscv_map_cache_event()