505 static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)  in ipic_read()  function
529 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_unmask_irq()
545 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_mask_irq()
584 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_mask_irq_and_ack()
642 	vold = ipic_read(ipic->regs, IPIC_SECNR);  in ipic_set_irq_type()
749 	temp = ipic_read(ipic->regs, IPIC_SEMSR);  in ipic_init()
782 	return primary_ipic ? ipic_read(primary_ipic->regs, IPIC_SERSR) : 0;  in ipic_get_mcp_status()
798 	irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;  in ipic_get_irq()
823 	ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);  in ipic_suspend()
824 	ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);  in ipic_suspend()
825 	ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);  in ipic_suspend()
826 	ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);  in ipic_suspend()
827 	ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);  in ipic_suspend()
828 	ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);  in ipic_suspend()
829 	ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);  in ipic_suspend()
830 	ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);  in ipic_suspend()
831 	ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);  in ipic_suspend()
832 	ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);  in ipic_suspend()
833 	ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);  in ipic_suspend()
834 	ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);  in ipic_suspend()