32 	setbits32(&rcpm_v1_regs->cpmimr, mask);  in rcpm_v1_irq_mask()
33 	setbits32(&rcpm_v1_regs->cpmcimr, mask);  in rcpm_v1_irq_mask()
34 	setbits32(&rcpm_v1_regs->cpmmcmr, mask);  in rcpm_v1_irq_mask()
35 	setbits32(&rcpm_v1_regs->cpmnmimr, mask);  in rcpm_v1_irq_mask()
43 	setbits32(&rcpm_v2_regs->tpmimr0, mask);  in rcpm_v2_irq_mask()
44 	setbits32(&rcpm_v2_regs->tpmcimr0, mask);  in rcpm_v2_irq_mask()
45 	setbits32(&rcpm_v2_regs->tpmmcmr0, mask);  in rcpm_v2_irq_mask()
46 	setbits32(&rcpm_v2_regs->tpmnmimr0, mask);  in rcpm_v2_irq_mask()
74 		setbits32(&rcpm_v1_regs->ippdexpcr, mask);  in rcpm_v1_set_ip_power()
82 		setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);  in rcpm_v2_set_ip_power()
94 		setbits32(&rcpm_v1_regs->cdozcr, mask);  in rcpm_v1_cpu_enter_state()
97 		setbits32(&rcpm_v1_regs->cnapcr, mask);  in rcpm_v1_cpu_enter_state()
113 		setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);  in rcpm_v2_cpu_enter_state()
116 		setbits32(&rcpm_v2_regs->pcph15setr, mask);  in rcpm_v2_cpu_enter_state()
119 		setbits32(&rcpm_v2_regs->pcph20setr, mask);  in rcpm_v2_cpu_enter_state()
122 		setbits32(&rcpm_v2_regs->pcph30setr, mask);  in rcpm_v2_cpu_enter_state()
195 		setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);  in rcpm_v2_cpu_exit_state()
198 		setbits32(&rcpm_v2_regs->pcph15clrr, mask);  in rcpm_v2_cpu_exit_state()
201 		setbits32(&rcpm_v2_regs->pcph20clrr, mask);  in rcpm_v2_cpu_exit_state()
204 		setbits32(&rcpm_v2_regs->pcph30clrr, mask);  in rcpm_v2_cpu_exit_state()
225 		setbits32(pmcsr_reg, RCPM_POWMGTCSR_SLP);  in rcpm_v1_plat_enter_state()
252 		setbits32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST);  in rcpm_v2_plat_enter_state()
254 		setbits32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ);  in rcpm_v2_plat_enter_state()
292 		setbits32(tben_reg, mask);  in rcpm_common_freeze_time_base()