Lines Matching refs:priv2
169 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_cntl() local
174 switch (in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
177 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
183 csa->priv2.mfc_control_RW = in save_mfc_cntl()
184 in_be64(&priv2->mfc_control_RW) | in save_mfc_cntl()
188 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE); in save_mfc_cntl()
189 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
193 csa->priv2.mfc_control_RW = in save_mfc_cntl()
194 in_be64(&priv2->mfc_control_RW) & in save_mfc_cntl()
249 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_stopped_status() local
259 csa->priv2.mfc_control_RW &= ~mask; in save_mfc_stopped_status()
260 csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask; in save_mfc_stopped_status()
265 struct spu_priv2 __iomem *priv2 = spu->priv2; in halt_mfc_decr() local
271 out_be64(&priv2->mfc_control_RW, in halt_mfc_decr()
335 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_queues() local
342 if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) { in save_mfc_queues()
344 csa->priv2.puq[i].mfc_cq_data0_RW = in save_mfc_queues()
345 in_be64(&priv2->puq[i].mfc_cq_data0_RW); in save_mfc_queues()
346 csa->priv2.puq[i].mfc_cq_data1_RW = in save_mfc_queues()
347 in_be64(&priv2->puq[i].mfc_cq_data1_RW); in save_mfc_queues()
348 csa->priv2.puq[i].mfc_cq_data2_RW = in save_mfc_queues()
349 in_be64(&priv2->puq[i].mfc_cq_data2_RW); in save_mfc_queues()
350 csa->priv2.puq[i].mfc_cq_data3_RW = in save_mfc_queues()
351 in_be64(&priv2->puq[i].mfc_cq_data3_RW); in save_mfc_queues()
354 csa->priv2.spuq[i].mfc_cq_data0_RW = in save_mfc_queues()
355 in_be64(&priv2->spuq[i].mfc_cq_data0_RW); in save_mfc_queues()
356 csa->priv2.spuq[i].mfc_cq_data1_RW = in save_mfc_queues()
357 in_be64(&priv2->spuq[i].mfc_cq_data1_RW); in save_mfc_queues()
358 csa->priv2.spuq[i].mfc_cq_data2_RW = in save_mfc_queues()
359 in_be64(&priv2->spuq[i].mfc_cq_data2_RW); in save_mfc_queues()
360 csa->priv2.spuq[i].mfc_cq_data3_RW = in save_mfc_queues()
361 in_be64(&priv2->spuq[i].mfc_cq_data3_RW); in save_mfc_queues()
403 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_csr_tsq() local
409 csa->priv2.spu_tag_status_query_RW = in save_mfc_csr_tsq()
410 in_be64(&priv2->spu_tag_status_query_RW); in save_mfc_csr_tsq()
415 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_csr_cmd() local
421 csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW); in save_mfc_csr_cmd()
422 csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW); in save_mfc_csr_cmd()
427 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_csr_ato() local
433 csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW); in save_mfc_csr_ato()
458 struct spu_priv2 __iomem *priv2 = spu->priv2; in purge_mfc_queue() local
464 out_be64(&priv2->mfc_control_RW, in purge_mfc_queue()
472 struct spu_priv2 __iomem *priv2 = spu->priv2; in wait_purge_complete() local
478 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in wait_purge_complete()
513 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_spu_privcntl() local
518 csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW); in save_spu_privcntl()
523 struct spu_priv2 __iomem *priv2 = spu->priv2; in reset_spu_privcntl() local
529 out_be64(&priv2->spu_privcntl_RW, 0UL); in reset_spu_privcntl()
535 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_spu_lslr() local
540 csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW); in save_spu_lslr()
545 struct spu_priv2 __iomem *priv2 = spu->priv2; in reset_spu_lslr() local
551 out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK); in reset_spu_lslr()
557 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_spu_cfg() local
562 csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW); in save_spu_cfg()
607 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_ppuint_mb() local
612 csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R); in save_ppuint_mb()
617 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_ch_part1() local
625 out_be64(&priv2->spu_chnlcntptr_RW, 1); in save_ch_part1()
626 csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW); in save_ch_part1()
631 out_be64(&priv2->spu_chnlcntptr_RW, idx); in save_ch_part1()
633 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW); in save_ch_part1()
634 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW); in save_ch_part1()
635 out_be64(&priv2->spu_chnldata_RW, 0UL); in save_ch_part1()
636 out_be64(&priv2->spu_chnlcnt_RW, 0UL); in save_ch_part1()
643 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_spu_mb() local
649 out_be64(&priv2->spu_chnlcntptr_RW, 29UL); in save_spu_mb()
651 csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW); in save_spu_mb()
653 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW); in save_spu_mb()
655 out_be64(&priv2->spu_chnlcnt_RW, 0UL); in save_spu_mb()
661 struct spu_priv2 __iomem *priv2 = spu->priv2; in save_mfc_cmd() local
666 out_be64(&priv2->spu_chnlcntptr_RW, 21UL); in save_mfc_cmd()
668 csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW); in save_mfc_cmd()
674 struct spu_priv2 __iomem *priv2 = spu->priv2; in reset_ch() local
685 out_be64(&priv2->spu_chnlcntptr_RW, idx); in reset_ch()
687 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); in reset_ch()
694 struct spu_priv2 __iomem *priv2 = spu->priv2; in resume_mfc_queue() local
700 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE); in resume_mfc_queue()
736 csa->priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND; in set_switch_active()
964 struct spu_priv2 __iomem *priv2 = spu->priv2; in suspend_mfc_and_halt_decr() local
970 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE | in suspend_mfc_and_halt_decr()
978 struct spu_priv2 __iomem *priv2 = spu->priv2; in wait_suspend_mfc_complete() local
984 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & in wait_suspend_mfc_complete()
1067 struct spu_priv2 __iomem *priv2 = spu->priv2; in reset_ch_part1() local
1076 out_be64(&priv2->spu_chnlcntptr_RW, 1); in reset_ch_part1()
1077 out_be64(&priv2->spu_chnldata_RW, 0UL); in reset_ch_part1()
1082 out_be64(&priv2->spu_chnlcntptr_RW, idx); in reset_ch_part1()
1084 out_be64(&priv2->spu_chnldata_RW, 0UL); in reset_ch_part1()
1085 out_be64(&priv2->spu_chnlcnt_RW, 0UL); in reset_ch_part1()
1092 struct spu_priv2 __iomem *priv2 = spu->priv2; in reset_ch_part2() local
1103 out_be64(&priv2->spu_chnlcntptr_RW, idx); in reset_ch_part2()
1105 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); in reset_ch_part2()
1263 if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) { in setup_decr()
1292 csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R; in setup_ppuint_mb()
1312 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_spu_privcntl() local
1317 out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW); in restore_spu_privcntl()
1386 struct spu_priv2 __iomem *priv2 = spu->priv2; in suspend_mfc() local
1392 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE); in suspend_mfc()
1418 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_mfc_queues() local
1425 if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) { in restore_mfc_queues()
1427 out_be64(&priv2->puq[i].mfc_cq_data0_RW, in restore_mfc_queues()
1428 csa->priv2.puq[i].mfc_cq_data0_RW); in restore_mfc_queues()
1429 out_be64(&priv2->puq[i].mfc_cq_data1_RW, in restore_mfc_queues()
1430 csa->priv2.puq[i].mfc_cq_data1_RW); in restore_mfc_queues()
1431 out_be64(&priv2->puq[i].mfc_cq_data2_RW, in restore_mfc_queues()
1432 csa->priv2.puq[i].mfc_cq_data2_RW); in restore_mfc_queues()
1433 out_be64(&priv2->puq[i].mfc_cq_data3_RW, in restore_mfc_queues()
1434 csa->priv2.puq[i].mfc_cq_data3_RW); in restore_mfc_queues()
1437 out_be64(&priv2->spuq[i].mfc_cq_data0_RW, in restore_mfc_queues()
1438 csa->priv2.spuq[i].mfc_cq_data0_RW); in restore_mfc_queues()
1439 out_be64(&priv2->spuq[i].mfc_cq_data1_RW, in restore_mfc_queues()
1440 csa->priv2.spuq[i].mfc_cq_data1_RW); in restore_mfc_queues()
1441 out_be64(&priv2->spuq[i].mfc_cq_data2_RW, in restore_mfc_queues()
1442 csa->priv2.spuq[i].mfc_cq_data2_RW); in restore_mfc_queues()
1443 out_be64(&priv2->spuq[i].mfc_cq_data3_RW, in restore_mfc_queues()
1444 csa->priv2.spuq[i].mfc_cq_data3_RW); in restore_mfc_queues()
1474 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_mfc_csr_tsq() local
1479 out_be64(&priv2->spu_tag_status_query_RW, in restore_mfc_csr_tsq()
1480 csa->priv2.spu_tag_status_query_RW); in restore_mfc_csr_tsq()
1486 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_mfc_csr_cmd() local
1492 out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW); in restore_mfc_csr_cmd()
1493 out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW); in restore_mfc_csr_cmd()
1499 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_mfc_csr_ato() local
1504 out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW); in restore_mfc_csr_ato()
1559 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_ch_part1() local
1568 out_be64(&priv2->spu_chnlcntptr_RW, idx); in restore_ch_part1()
1570 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]); in restore_ch_part1()
1571 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]); in restore_ch_part1()
1578 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_ch_part2() local
1592 out_be64(&priv2->spu_chnlcntptr_RW, idx); in restore_ch_part2()
1594 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); in restore_ch_part2()
1601 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_spu_lslr() local
1606 out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW); in restore_spu_lslr()
1612 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_spu_cfg() local
1617 out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW); in restore_spu_cfg()
1642 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_spu_mb() local
1648 out_be64(&priv2->spu_chnlcntptr_RW, 29UL); in restore_spu_mb()
1650 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]); in restore_spu_mb()
1652 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]); in restore_spu_mb()
1674 struct spu_priv2 __iomem *priv2 = spu->priv2; in check_ppuint_mb_stat() local
1682 dummy = in_be64(&priv2->puint_mb_R); in check_ppuint_mb_stat()
1729 struct spu_priv2 __iomem *priv2 = spu->priv2; in restore_mfc_cntl() local
1734 out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW); in restore_mfc_cntl()
1876 struct spu_priv2 __iomem *priv2 = spu->priv2; in force_spu_isolate_exit() local
1888 out_be64(&priv2->spu_privcntl_RW, 4LL); in force_spu_isolate_exit()
1896 out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL); in force_spu_isolate_exit()
2167 csa->priv2.spu_lslr_RW = LS_ADDR_MASK; in init_priv2()
2168 csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE | in init_priv2()