Lines Matching refs:priv1
112 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0); in disable_interrupts()
113 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1); in disable_interrupts()
114 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2); in disable_interrupts()
217 csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu); in save_mfc_sr1()
442 csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu); in save_mfc_tclass_id()
579 csa->priv1.resource_allocation_groupID_RW = in save_mfc_rag()
581 csa->priv1.resource_allocation_enable_RW = in save_mfc_rag()
1233 csa->priv1.resource_allocation_groupID_RW); in restore_mfc_rag()
1235 csa->priv1.resource_allocation_enable_RW); in restore_mfc_rag()
1512 spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW); in restore_mfc_tclass_id()
1694 spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW); in restore_mfc_sr1()
1771 spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW); in reenable_interrupts()
1772 spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW); in reenable_interrupts()
1773 spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW); in reenable_interrupts()
2149 csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK | in init_priv1()
2155 csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR | in init_priv1()
2158 csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR | in init_priv1()
2160 csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR | in init_priv1()