188 		out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);  in save_mfc_cntl()
271 	out_be64(&priv2->mfc_control_RW,  in halt_mfc_decr()
303 	out_be64(&prob->spc_mssync_RW, 1UL);  in do_mfc_mssync()
464 	out_be64(&priv2->mfc_control_RW,  in purge_mfc_queue()
529 	out_be64(&priv2->spu_privcntl_RW, 0UL);  in reset_spu_privcntl()
551 	out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);  in reset_spu_lslr()
625 	out_be64(&priv2->spu_chnlcntptr_RW, 1);  in save_ch_part1()
631 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in save_ch_part1()
635 		out_be64(&priv2->spu_chnldata_RW, 0UL);  in save_ch_part1()
636 		out_be64(&priv2->spu_chnlcnt_RW, 0UL);  in save_ch_part1()
649 	out_be64(&priv2->spu_chnlcntptr_RW, 29UL);  in save_spu_mb()
655 	out_be64(&priv2->spu_chnlcnt_RW, 0UL);  in save_spu_mb()
666 	out_be64(&priv2->spu_chnlcntptr_RW, 21UL);  in save_mfc_cmd()
685 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in reset_ch()
687 		out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);  in reset_ch()
700 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);  in resume_mfc_queue()
783 			out_be64(&prob->mfc_ea_W, ea);  in send_mfc_dma()
784 			out_be64(&prob->mfc_union_W.all64, command.all64);  in send_mfc_dma()
970 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |  in suspend_mfc_and_halt_decr()
1076 	out_be64(&priv2->spu_chnlcntptr_RW, 1);  in reset_ch_part1()
1077 	out_be64(&priv2->spu_chnldata_RW, 0UL);  in reset_ch_part1()
1082 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in reset_ch_part1()
1084 		out_be64(&priv2->spu_chnldata_RW, 0UL);  in reset_ch_part1()
1085 		out_be64(&priv2->spu_chnlcnt_RW, 0UL);  in reset_ch_part1()
1103 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in reset_ch_part2()
1105 		out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);  in reset_ch_part2()
1317 	out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);  in restore_spu_privcntl()
1392 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);  in suspend_mfc()
1427 			out_be64(&priv2->puq[i].mfc_cq_data0_RW,  in restore_mfc_queues()
1429 			out_be64(&priv2->puq[i].mfc_cq_data1_RW,  in restore_mfc_queues()
1431 			out_be64(&priv2->puq[i].mfc_cq_data2_RW,  in restore_mfc_queues()
1433 			out_be64(&priv2->puq[i].mfc_cq_data3_RW,  in restore_mfc_queues()
1437 			out_be64(&priv2->spuq[i].mfc_cq_data0_RW,  in restore_mfc_queues()
1439 			out_be64(&priv2->spuq[i].mfc_cq_data1_RW,  in restore_mfc_queues()
1441 			out_be64(&priv2->spuq[i].mfc_cq_data2_RW,  in restore_mfc_queues()
1443 			out_be64(&priv2->spuq[i].mfc_cq_data3_RW,  in restore_mfc_queues()
1479 	out_be64(&priv2->spu_tag_status_query_RW,  in restore_mfc_csr_tsq()
1492 	out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);  in restore_mfc_csr_cmd()
1493 	out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);  in restore_mfc_csr_cmd()
1504 	out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);  in restore_mfc_csr_ato()
1568 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in restore_ch_part1()
1570 		out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);  in restore_ch_part1()
1571 		out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);  in restore_ch_part1()
1592 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in restore_ch_part2()
1594 		out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);  in restore_ch_part2()
1606 	out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);  in restore_spu_lslr()
1617 	out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);  in restore_spu_cfg()
1648 	out_be64(&priv2->spu_chnlcntptr_RW, 29UL);  in restore_spu_mb()
1650 	out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);  in restore_spu_mb()
1652 		out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);  in restore_spu_mb()
1734 	out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);  in restore_mfc_cntl()
1888 	out_be64(&priv2->spu_privcntl_RW, 4LL);  in force_spu_isolate_exit()
1896 	out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);  in force_spu_isolate_exit()