31 	old_mask = in_be64(&spu->priv1->int_mask_RW[class]);  in int_mask_and()
32 	out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);  in int_mask_and()
39 	old_mask = in_be64(&spu->priv1->int_mask_RW[class]);  in int_mask_or()
40 	out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);  in int_mask_or()
45 	out_be64(&spu->priv1->int_mask_RW[class], mask);  in int_mask_set()
50 	return in_be64(&spu->priv1->int_mask_RW[class]);  in int_mask_get()
55 	out_be64(&spu->priv1->int_stat_RW[class], stat);  in int_stat_clear()
60 	return in_be64(&spu->priv1->int_stat_RW[class]);  in int_stat_get()
78 	out_be64(&spu->priv1->int_route_RW, route);  in cpu_affinity_set()
83 	return in_be64(&spu->priv1->mfc_dar_RW);  in mfc_dar_get()
88 	return in_be64(&spu->priv1->mfc_dsisr_RW);  in mfc_dsisr_get()
93 	out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);  in mfc_dsisr_set()
98 	out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));  in mfc_sdr_setup()
103 	out_be64(&spu->priv1->mfc_sr1_RW, sr1);  in mfc_sr1_set()
108 	return in_be64(&spu->priv1->mfc_sr1_RW);  in mfc_sr1_get()
113 	out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);  in mfc_tclass_id_set()
118 	return in_be64(&spu->priv1->mfc_tclass_id_RW);  in mfc_tclass_id_get()
123 	out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);  in tlb_invalidate()
128 	out_be64(&spu->priv1->resource_allocation_groupID_RW, id);  in resource_allocation_groupID_set()
133 	return in_be64(&spu->priv1->resource_allocation_groupID_RW);  in resource_allocation_groupID_get()
138 	out_be64(&spu->priv1->resource_allocation_enable_RW, enable);  in resource_allocation_enable_set()
143 	return in_be64(&spu->priv1->resource_allocation_enable_RW);  in resource_allocation_enable_get()