Lines Matching refs:r3
44 stw r3, THREAD+KSP_LIMIT(r2)
45 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
46 mr r1,r3
80 cmpwi cr1,r3,0
89 mullw r9,r3,r5
90 mulhwu r10,r3,r5
92 mullw r0,r3,r6
93 mulhwu r8,r3,r6
98 addze r3,r10
122 add r0,r0,r3
138 addis r4,r3,cur_cpu_spec@ha
141 add r4,r4,r3
144 add r5,r5,r3
162 cmplwi cr0,r3,0
174 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
190 cmplwi cr0,r3,0
212 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
230 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
249 lbz r3,0(r3)
266 stb r3,0(r4)
284 li r3, 512
285 mtctr r3
291 lis r3, KERNELBASE@h
292 iccci 0,r3
296 mfspr r3,SPRN_L1CSR0
297 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
299 mtspr SPRN_L1CSR0,r3
303 mfspr r3,SPRN_L1CSR1
304 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
305 mtspr SPRN_L1CSR1,r3
310 mfspr r3,SPRN_HID0
311 ori r3,r3,HID0_ICFI
312 mtspr SPRN_HID0,r3
331 rlwinm r3,r3,0,0,31 - L1_CACHE_SHIFT
332 subf r4,r3,r4
337 mr r6,r3
338 1: dcbst 0,r3
339 addi r3,r3,L1_CACHE_BYTES
373 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
376 mr r6,r3
377 0: dcbst 0,r3 /* Write line to ram */
378 addi r3,r3,L1_CACHE_BYTES
420 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
423 mr r6,r3
424 0: dcbst 0,r3 /* Write line to ram */
425 addi r3,r3,L1_CACHE_BYTES
450 stw r6,4(r3); \
451 stw r7,8(r3); \
452 stw r8,12(r3); \
453 stwu r9,16(r3)
456 rlwinm r5, r3, 0, L1_CACHE_BYTES - 1
457 addi r3,r3,-4
483 dcbz r5,r3
524 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
526 sraw r7,r3,r7 # t2 = MSW >> (count-32)
529 sraw r3,r3,r5 # MSW = MSW >> count
536 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
540 or r3,r3,r6 # MSW |= t1
542 or r3,r3,r7 # MSW |= t2
550 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
551 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
553 srw r3,r3,r5 # MSW = MSW >> count
563 cmpw r3,r5
564 li r3,1
568 1: li r3,0
570 li r3,2
578 cmplw r3,r5
579 li r3,1
583 1: li r3,0
585 li r3,2
591 rotlwi r10,r3,8
593 rlwimi r10,r3,24,0,7
595 rlwimi r10,r3,24,16,23
596 mr r3,r9
606 li r3,0
607 stw r3,0(r1) /* Zero the stack frame pointer */
630 mr r29, r3
638 mr r3, r29
646 mr r29, r3
652 mfspr r3,SPRN_PVR
653 srwi r3,r3,16
654 cmplwi cr0,r3,PVR_476FPE@h
656 cmplwi cr0,r3,PVR_476@h
658 cmplwi cr0,r3,PVR_476_ISS@h
682 li r3, 0
683 mtspr SPRN_PID, r3
687 oris r3,r3,PPC44x_MMUCR_STS@h
689 mtspr SPRN_MMUCR,r3
700 li r3,0 /* Set PAGEID inval value */
703 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
719 tlbre r3, r23, PPC44x_TLB_PAGEID
728 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
748 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
751 tlbwe r3, r24, PPC44x_TLB_PAGEID
772 li r3, 0
773 tlbwe r3, r23, PPC44x_TLB_PAGEID
786 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
787 mr r4, r3 /* RPN = EPN */
788 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
789 insrwi r3, r7, 1, 23 /* Set TS from r7 */
791 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
818 li r3, 0
819 tlbwe r3, r24, PPC44x_TLB_PAGEID
833 li r3, 0
834 mtspr SPRN_PID, r3 /* Set PID */
838 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
839 1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
858 addis r3, 0, 0x8000 /* specify the way */
868 tlbwe r4, r3, 0
869 tlbwe r5, r3, 1
870 tlbwe r5, r3, 2
871 addis r3, r3, 0x2000 /* Increment the way */
872 cmpwi r3, 0
874 addis r3, 0, 0x8000
890 lis r3, 0x8000 /* Way '0' */
892 tlbwe r24, r3, 0
893 tlbwe r25, r3, 1
894 tlbwe r26, r3, 2
912 li r3, 0
930 tlbwe r4, r3, 0 /* Write out the entries */
931 tlbwe r5, r3, 1
932 tlbwe r6, r3, 2
980 lis r3, 0x8000 /* Way '0' */
983 tlbwe r24, r3, 0
984 tlbwe r25, r3, 1
985 tlbwe r26, r3, 2
996 mr r3, r29
1029 mr r0, r3
1033 lwzu r0, 4(r3)
1047 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
1048 subi r3, r3, 4
1087 mfspr r3, SPRN_PIR /* current core we are running on */