Lines Matching refs:uint
57 extern void cpm_setbrg(uint brg, uint rate);
65 #define PROFF_SCC1 ((uint)0x0000)
66 #define PROFF_IIC ((uint)0x0080)
67 #define PROFF_SCC2 ((uint)0x0100)
68 #define PROFF_SPI ((uint)0x0180)
69 #define PROFF_SCC3 ((uint)0x0200)
70 #define PROFF_SMC1 ((uint)0x0280)
71 #define PROFF_SCC4 ((uint)0x0300)
72 #define PROFF_SMC2 ((uint)0x0380)
83 uint smc_rstate; /* Internal */
84 uint smc_idp; /* Internal */
87 uint smc_rxtmp; /* Internal */
88 uint smc_tstate; /* Internal */
89 uint smc_tdp; /* Internal */
92 uint smc_txtmp; /* Internal */
135 uint scent_rstate;
136 uint scent_r_ptr;
139 uint scent_rtemp;
140 uint scent_tstate;
141 uint scent_t_ptr;
144 uint scent_ttemp;
176 #define CPM_BRG_RST ((uint)0x00020000)
177 #define CPM_BRG_EN ((uint)0x00010000)
178 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
179 #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
180 #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
181 #define CPM_BRG_ATB ((uint)0x00002000)
182 #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
183 #define CPM_BRG_DIV16 ((uint)0x00000001)
187 #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
188 #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
189 #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
190 #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
191 #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
192 #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
193 #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
194 #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
198 #define SCC_GSMRH_IRP ((uint)0x00040000)
199 #define SCC_GSMRH_GDE ((uint)0x00010000)
200 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
201 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
202 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
203 #define SCC_GSMRH_REVD ((uint)0x00002000)
204 #define SCC_GSMRH_TRX ((uint)0x00001000)
205 #define SCC_GSMRH_TTX ((uint)0x00000800)
206 #define SCC_GSMRH_CDP ((uint)0x00000400)
207 #define SCC_GSMRH_CTSP ((uint)0x00000200)
208 #define SCC_GSMRH_CDS ((uint)0x00000100)
209 #define SCC_GSMRH_CTSS ((uint)0x00000080)
210 #define SCC_GSMRH_TFL ((uint)0x00000040)
211 #define SCC_GSMRH_RFW ((uint)0x00000020)
212 #define SCC_GSMRH_TXSY ((uint)0x00000010)
213 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
214 #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
215 #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
216 #define SCC_GSMRH_RTSM ((uint)0x00000002)
217 #define SCC_GSMRH_RSYN ((uint)0x00000001)
219 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
220 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
221 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
222 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
223 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
224 #define SCC_GSMRL_TCI ((uint)0x10000000)
225 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
226 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
227 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
228 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
229 #define SCC_GSMRL_RINV ((uint)0x02000000)
230 #define SCC_GSMRL_TINV ((uint)0x01000000)
231 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
232 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
233 #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
234 #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
235 #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
236 #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
237 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
238 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
239 #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
240 #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
241 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
242 #define SCC_GSMRL_TEND ((uint)0x00040000)
243 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
244 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
245 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
246 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
247 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
248 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
249 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
250 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
251 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
252 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
253 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
254 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
255 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
256 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
257 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
258 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
259 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
260 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
261 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
262 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
263 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
264 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
265 #define SCC_GSMRL_ENR ((uint)0x00000020)
266 #define SCC_GSMRL_ENT ((uint)0x00000010)
267 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
268 #define SCC_GSMRL_MODE_QMC ((uint)0x0000000a)
269 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
270 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
271 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
272 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
273 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
274 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
275 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
276 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
277 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
294 uint scc_rstate; /* Internal */
295 uint scc_idp; /* Internal */
298 uint scc_rxtmp; /* Internal */
299 uint scc_tstate; /* Internal */
300 uint scc_tdp; /* Internal */
303 uint scc_txtmp; /* Internal */
304 uint scc_rcrc; /* Internal */
305 uint scc_tcrc; /* Internal */
316 uint sen_cpres; /* Preset CRC */
317 uint sen_cmask; /* Constant mask for CRC */
318 uint sen_crcec; /* CRC Error counter */
319 uint sen_alec; /* alignment error counter */
320 uint sen_disfc; /* discard frame counter */
335 uint sen_tbuf0data0; /* Save area 0 - current frame */
336 uint sen_tbuf0data1; /* Save area 1 - current frame */
337 uint sen_tbuf0rba; /* Internal */
338 uint sen_tbuf0crc; /* Internal */
347 uint sen_tbuf1data0; /* Save area 0 - current frame */
348 uint sen_tbuf1data1; /* Save area 1 - current frame */
349 uint sen_tbuf1rba; /* Internal */
350 uint sen_tbuf1crc; /* Internal */
456 uint st_cpres; /* Preset CRC */
457 uint st_cmask; /* Constant mask for CRC */
468 uint iic_rstate; /* Internal */
469 uint iic_rdp; /* Internal */
472 uint iic_rxtmp; /* Internal */
473 uint iic_tstate; /* Internal */
474 uint iic_tdp; /* Internal */
477 uint iic_txtmp; /* Internal */
491 #define PROFF_RTMR ((uint)0x01B0)
549 #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
550 #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
551 #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
552 #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
553 #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
554 #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
555 #define CICR_IEN ((uint)0x00000080) /* Int. enable */
556 #define CICR_SPS ((uint)0x00000001) /* SCC Spread */