Lines Matching +full:ethernet +full:- +full:phy
4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
75 qman_pfdr: qman-pfdr {
85 bportals: bman-portals@ff4000000 {
89 qportals: qman-portals@ff4200000 {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "spansion,s25sl12801", "jedec,spi-nor";
103 spi-max-frequency = <40000000>; /* input clock */
104 partition@u-boot {
105 label = "u-boot";
107 read-only;
112 read-only;
117 read-only;
156 ethernet@e0000 {
157 phy-handle = <&phy0>;
158 phy-connection-type = "sgmii";
161 ethernet@e2000 {
162 phy-handle = <&phy1>;
163 phy-connection-type = "sgmii";
166 ethernet@e4000 {
167 phy-handle = <&phy2>;
168 phy-connection-type = "sgmii";
171 ethernet@e6000 {
172 phy-handle = <&phy3>;
173 phy-connection-type = "sgmii";
176 ethernet@f0000 {
177 phy-handle = <&phy10>;
178 phy-connection-type = "xgmii";
183 ethernet@e0000 {
184 phy-handle = <&phy5>;
185 phy-connection-type = "sgmii";
188 ethernet@e2000 {
189 phy-handle = <&phy6>;
190 phy-connection-type = "sgmii";
193 ethernet@e4000 {
194 phy-handle = <&phy7>;
195 phy-connection-type = "sgmii";
198 ethernet@e6000 {
199 phy-handle = <&phy8>;
200 phy-connection-type = "sgmii";
203 ethernet@f0000 {
204 phy-handle = <&phy11>;
205 phy-connection-type = "xgmii";
227 compatible = "cfi-flash";
229 bank-width = <2>;
230 device-width = <2>;
233 board-control@3,0 {
234 compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis";
284 mdio-mux-emi1 {
285 #address-cells = <1>;
286 #size-cells = <0>;
287 compatible = "mdio-mux-gpio", "mdio-mux";
288 mdio-parent-bus = <&mdio0>;
292 #address-cells = <1>;
293 #size-cells = <0>;
296 phyrgmii: ethernet-phy@0 {
302 #address-cells = <1>;
303 #size-cells = <0>;
306 phy5: ethernet-phy@1c {
310 phy6: ethernet-phy@1d {
314 phy7: ethernet-phy@1e {
318 phy8: ethernet-phy@1f {
324 #address-cells = <1>;
325 #size-cells = <0>;
329 phy5slot3: ethernet-phy@1c {
333 phy6slot3: ethernet-phy@1d {
337 phy7slot3: ethernet-phy@1e {
341 phy8slot3: ethernet-phy@1f {
347 #address-cells = <1>;
348 #size-cells = <0>;
351 phy0: ethernet-phy@1c {
355 phy1: ethernet-phy@1d {
359 phy2: ethernet-phy@1e {
363 phy3: ethernet-phy@1f {
369 mdio-mux-emi2 {
370 #address-cells = <1>;
371 #size-cells = <0>;
372 compatible = "mdio-mux-gpio", "mdio-mux";
373 mdio-parent-bus = <&xmdio0>;
377 #address-cells = <1>;
378 #size-cells = <0>;
381 phy11: ethernet-phy@0 {
382 compatible = "ethernet-phy-ieee802.3-c45";
388 #address-cells = <1>;
389 #size-cells = <0>;
392 phy10: ethernet-phy@4 {
393 compatible = "ethernet-phy-ieee802.3-c45";
400 /include/ "p4080si-post.dtsi"