Lines Matching refs:ori
38 l.ori gpr,gpr,lo(symbol)
265 l.ori r30,r30,(EXCEPTION_SR) ;\
302 l.ori r3,r0,lo(_string_unhandled_exception) ;\
308 l.ori r3,r0,lo(_string_epc_prefix) ;\
312 l.ori r3,r0,lo(_string_nl) ;\
347 l.ori r30,r0,(EXCEPTION_SR) ;\
521 l.ori r3,r0,0x1
570 l.ori r4,r0,0x0
611 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
637 l.ori r4,r4,lo(OF_DT_HEADER)
729 l.ori r25,r25,SPR_SR_IEE
734 l.ori r25,r25,0xffff
785 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
836 l.ori r30,r0,16
845 l.ori r30,r0,1
863 l.ori r6,r6,SPR_SR_ICE
902 l.ori r30,r0,16
911 l.ori r30,r0,1
925 l.ori r6,r6,SPR_SR_DCE
997 l.ori r5, r0, 0x1
1003 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1005 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1017 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1019 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1084 l.ori r5, r0, 0x1
1090 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1092 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1110 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1112 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1197 l.ori r3, r0, 0x1
1209 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1282 l.ori r3, r0, 0x1
1297 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1304 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1393 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1399 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1444 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1450 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1457 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1523 l.ori r23,r0,16
1690 l.ori r4,r5,0x80
1707 l.ori r3,r0,SPR_SR_SM