186 	struct hw_perf_event *hwc = &event->hw;  in nds32_pmu_event_set_period()  local
187 	s64 left = local64_read(&hwc->period_left);  in nds32_pmu_event_set_period()
188 	s64 period = hwc->sample_period;  in nds32_pmu_event_set_period()
192 	if (unlikely(period != hwc->last_period))  in nds32_pmu_event_set_period()
193 		left = period - (hwc->last_period - left);  in nds32_pmu_event_set_period()
197 		local64_set(&hwc->period_left, left);  in nds32_pmu_event_set_period()
198 		hwc->last_period = period;  in nds32_pmu_event_set_period()
204 		local64_set(&hwc->period_left, left);  in nds32_pmu_event_set_period()
205 		hwc->last_period = period;  in nds32_pmu_event_set_period()
216 	local64_set(&hwc->prev_count, (u64)(-left));  in nds32_pmu_event_set_period()
252 		struct hw_perf_event *hwc;  in nds32_pmu_handle_irq()  local
265 		hwc = &event->hw;  in nds32_pmu_handle_irq()
267 		perf_sample_data_init(&data, 0, hwc->last_period);  in nds32_pmu_handle_irq()
416 	struct hw_perf_event *hwc = &event->hw;  in nds32_pmu_enable_event()  local
419 	int idx = hwc->idx;  in nds32_pmu_enable_event()
441 	     cpu_pmu->set_event_filter(hwc, &event->attr)) &&  in nds32_pmu_enable_event()
445 		hwc->config_base = 0;  in nds32_pmu_enable_event()
448 	evnum = hwc->config_base;  in nds32_pmu_enable_event()
467 	struct hw_perf_event *hwc = &event->hw;  in nds32_pmu_disable_event()  local
470 	int idx = hwc->idx;  in nds32_pmu_disable_event()
498 	struct hw_perf_event *hwc = &event->hw;  in nds32_pmu_read_counter()  local
499 	int idx = hwc->idx;  in nds32_pmu_read_counter()
527 	struct hw_perf_event *hwc = &event->hw;  in nds32_pmu_write_counter()  local
528 	int idx = hwc->idx;  in nds32_pmu_write_counter()
555 	struct hw_perf_event *hwc = &event->hw;  in nds32_pmu_get_event_idx()  local
567 	unsigned long evtype = hwc->config_base & SOFTWARE_EVENT_MASK;  in nds32_pmu_get_event_idx()
799 	struct hw_perf_event *hwc = &event->hw;  in __hw_perf_event_init()  local
816 	hwc->idx = -1;  in __hw_perf_event_init()
817 	hwc->config_base = 0;  in __hw_perf_event_init()
818 	hwc->config = 0;  in __hw_perf_event_init()
819 	hwc->event_base = 0;  in __hw_perf_event_init()
825 	     nds32_pmu->set_event_filter(hwc, &event->attr)) &&  in __hw_perf_event_init()
835 	hwc->config_base |= (unsigned long)mapping;  in __hw_perf_event_init()
837 	if (!hwc->sample_period) {  in __hw_perf_event_init()
844 		hwc->sample_period = nds32_pmu->max_period >> 1;  in __hw_perf_event_init()
845 		hwc->last_period = hwc->sample_period;  in __hw_perf_event_init()
846 		local64_set(&hwc->period_left, hwc->sample_period);  in __hw_perf_event_init()
891 	struct hw_perf_event *hwc = &event->hw;  in nds32_start()  local
897 		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));  in nds32_start()
899 	hwc->state = 0;  in nds32_start()
910 	struct hw_perf_event *hwc = &event->hw;  in nds32_pmu_add()  local
931 	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;  in nds32_pmu_add()
946 	struct hw_perf_event *hwc = &event->hw;  in nds32_pmu_event_update()  local
950 	prev_raw_count = local64_read(&hwc->prev_count);  in nds32_pmu_event_update()
953 	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,  in nds32_pmu_event_update()
964 	local64_sub(delta, &hwc->period_left);  in nds32_pmu_event_update()
972 	struct hw_perf_event *hwc = &event->hw;  in nds32_stop()  local
977 	if (!(hwc->state & PERF_HES_STOPPED)) {  in nds32_stop()
980 		hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;  in nds32_stop()
988 	struct hw_perf_event *hwc = &event->hw;  in nds32_pmu_del()  local
989 	int idx = hwc->idx;  in nds32_pmu_del()