286 				    struct hw_perf_event *hwc)  in mipsxx_pmu_alloc_counter()  argument
294 	unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;  in mipsxx_pmu_alloc_counter()
371 				    struct hw_perf_event *hwc,  in mipspmu_event_set_period()  argument
374 	u64 left = local64_read(&hwc->period_left);  in mipspmu_event_set_period()
375 	u64 period = hwc->sample_period;  in mipspmu_event_set_period()
381 		local64_set(&hwc->period_left, left);  in mipspmu_event_set_period()
382 		hwc->last_period = period;  in mipspmu_event_set_period()
387 		local64_set(&hwc->period_left, left);  in mipspmu_event_set_period()
388 		hwc->last_period = period;  in mipspmu_event_set_period()
394 		local64_set(&hwc->period_left, left);  in mipspmu_event_set_period()
397 	local64_set(&hwc->prev_count, mipspmu.overflow - left);  in mipspmu_event_set_period()
407 				 struct hw_perf_event *hwc,  in mipspmu_event_update()  argument
414 	prev_raw_count = local64_read(&hwc->prev_count);  in mipspmu_event_update()
417 	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,  in mipspmu_event_update()
424 	local64_sub(delta, &hwc->period_left);  in mipspmu_event_update()
429 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_start()  local
432 		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));  in mipspmu_start()
434 	hwc->state = 0;  in mipspmu_start()
437 	mipspmu_event_set_period(event, hwc, hwc->idx);  in mipspmu_start()
440 	mipsxx_pmu_enable_event(hwc, hwc->idx);  in mipspmu_start()
445 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_stop()  local
447 	if (!(hwc->state & PERF_HES_STOPPED)) {  in mipspmu_stop()
449 		mipsxx_pmu_disable_event(hwc->idx);  in mipspmu_stop()
451 		mipspmu_event_update(event, hwc, hwc->idx);  in mipspmu_stop()
452 		hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;  in mipspmu_stop()
459 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_add()  local
466 	idx = mipsxx_pmu_alloc_counter(cpuc, hwc);  in mipspmu_add()
480 	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;  in mipspmu_add()
495 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_del()  local
496 	int idx = hwc->idx;  in mipspmu_del()
509 	struct hw_perf_event *hwc = &event->hw;  in mipspmu_read()  local
512 	if (hwc->idx < 0)  in mipspmu_read()
515 	mipspmu_event_update(event, hwc, hwc->idx);  in mipspmu_read()
738 	struct hw_perf_event *hwc = &event->hw;  in handle_associated_event()  local
740 	mipspmu_event_update(event, hwc, idx);  in handle_associated_event()
742 	if (!mipspmu_event_set_period(event, hwc, idx))  in handle_associated_event()
1282 	struct hw_perf_event *hwc = &event->hw;  in __hw_perf_event_init()  local
1312 	hwc->config_base = MIPS_PERFCTRL_IE;  in __hw_perf_event_init()
1314 	hwc->event_base = mipspmu_perf_event_encode(pev);  in __hw_perf_event_init()
1319 		hwc->config_base |= MIPS_PERFCTRL_U;  in __hw_perf_event_init()
1321 		hwc->config_base |= MIPS_PERFCTRL_K;  in __hw_perf_event_init()
1323 		hwc->config_base |= MIPS_PERFCTRL_EXL;  in __hw_perf_event_init()
1326 		hwc->config_base |= MIPS_PERFCTRL_S;  in __hw_perf_event_init()
1328 	hwc->config_base &= M_PERFCTL_CONFIG_MASK;  in __hw_perf_event_init()
1333 	hwc->idx = -1;  in __hw_perf_event_init()
1334 	hwc->config = 0;  in __hw_perf_event_init()
1336 	if (!hwc->sample_period) {  in __hw_perf_event_init()
1337 		hwc->sample_period  = mipspmu.max_period;  in __hw_perf_event_init()
1338 		hwc->last_period    = hwc->sample_period;  in __hw_perf_event_init()
1339 		local64_set(&hwc->period_left, hwc->sample_period);  in __hw_perf_event_init()