Lines Matching refs:T
65 T = 0, enumerator
813 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
814 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
815 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
822 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
823 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
824 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
856 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
857 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
858 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
883 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
884 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
887 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
888 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
893 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
894 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
897 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
898 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
901 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
920 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
921 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
924 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
925 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
930 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
931 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
934 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
935 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
941 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
942 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
945 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
946 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
964 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
965 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
968 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
969 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
974 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
975 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
978 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
979 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
982 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
1006 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1007 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1010 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1011 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1017 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1018 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1021 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1022 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1135 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1136 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1139 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1140 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1145 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1146 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1149 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1150 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1153 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },
1173 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1176 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1545 raw_event.range = T; in mipsxx_pmu_map_raw_event()
1601 raw_event.range = T; in mipsxx_pmu_map_raw_event()
1616 raw_event.range = T; in mipsxx_pmu_map_raw_event()