Lines Matching +full:implementation +full:- +full:defined

6  * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
14  * Sync types defined by the MIPS architecture (document MD00087 table 6.5)
17  * - Completion Barriers
18  * - Ordering Barriers
20  * lighter-weight operation as it does not require the specified instructions
23  * stream are never re-ordered for processing ahead of the specified
27  * Implementations that do not use any of the non-zero values of stype to define
34  * - Every synchronizable specified memory instruction (loads or stores or both)
40  * - The barrier does not guarantee the order in which instruction fetches are
43  * - A stype value of zero will always be defined such that it performs the most
44  *   complete set of synchronization operations that are defined.This means
47  *   subsequent to the SYNC instruction. Non-zero values of stype may be defined
50  *   implementation does not use one of these non-zero values to define a
51  *   different synchronization behavior, then that non-zero value of stype must
53  *   for an implementation with a lighter-weight barrier to work on another
54  *   implementation which only implements the stype zero completion barrier.
56  * - A completion barrier is required, potentially in conjunction with SSNOP (in
65  * stype 0 - A completion barrier that affects preceding loads and stores and
78  * - Every synchronizable specified memory instruction (loads or stores or both)
81  *   re-ordering is possible before any synchronizable specified memory
85  * - If any memory instruction before the SYNC instruction in program order,
92  * - The barrier does not guarantee the order in which instruction fetches are
97  * stype 0x10 - An ordering barrier that affects preceding loads and stores and
109  * stype 0x14 - A completion barrier specific to global invalidations
114  * all coherent CPUs when this instruction completes. It is implementation
198 #if defined(CONFIG_WEAK_ORDERING)
220 #if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
255  *    be executed after the LL - this is the reordering case.
264  *    of the LL-SC loop, for example an exit upon value mismatch in cmpxchg()
266  *    execution of memory accesses from outside of the LL-SC loop.
270  *    defined below.
275  * such that the Invalidate of a competing LL-SC goes 'missing' and SC
281 #ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS /* Loongson-3's LLSC workaround */
292 #include <asm-generic/barrier.h>