93 static void __init ar71xx_clocks_init(void __iomem *pll_base)  in ar71xx_clocks_init()  argument
105 	pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);  in ar71xx_clocks_init()
124 static void __init ar724x_clocks_init(void __iomem *pll_base)  in ar724x_clocks_init()  argument
131 	pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);  in ar724x_clocks_init()
144 static void __init ar933x_clocks_init(void __iomem *pll_base)  in ar933x_clocks_init()  argument
165 	clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);  in ar933x_clocks_init()
178 		cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);  in ar933x_clocks_init()
232 static void __init ar934x_clocks_init(void __iomem *pll_base)  in ar934x_clocks_init()  argument
265 		pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);  in ar934x_clocks_init()
292 		pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);  in ar934x_clocks_init()
307 	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);  in ar934x_clocks_init()
343 	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);  in ar934x_clocks_init()
350 static void __init qca953x_clocks_init(void __iomem *pll_base)  in qca953x_clocks_init()  argument
368 	pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);  in qca953x_clocks_init()
382 	pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);  in qca953x_clocks_init()
396 	clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);  in qca953x_clocks_init()
433 static void __init qca955x_clocks_init(void __iomem *pll_base)  in qca955x_clocks_init()  argument
451 	pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);  in qca955x_clocks_init()
465 	pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);  in qca955x_clocks_init()
479 	clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);  in qca955x_clocks_init()
516 static void __init qca956x_clocks_init(void __iomem *pll_base)  in qca956x_clocks_init()  argument
544 	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);  in qca956x_clocks_init()
550 	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);  in qca956x_clocks_init()
563 	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);  in qca956x_clocks_init()
568 	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);  in qca956x_clocks_init()
581 	clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);  in qca956x_clocks_init()
621 	void __iomem *pll_base;  in ath79_clocks_init_dt()  local
627 	pll_base = of_iomap(np, 0);  in ath79_clocks_init_dt()
628 	if (!pll_base) {  in ath79_clocks_init_dt()
634 		ar71xx_clocks_init(pll_base);  in ath79_clocks_init_dt()
637 		ar724x_clocks_init(pll_base);  in ath79_clocks_init_dt()
639 		ar933x_clocks_init(pll_base);  in ath79_clocks_init_dt()
641 		ar934x_clocks_init(pll_base);  in ath79_clocks_init_dt()
643 		qca953x_clocks_init(pll_base);  in ath79_clocks_init_dt()
645 		qca955x_clocks_init(pll_base);  in ath79_clocks_init_dt()
647 		qca956x_clocks_init(pll_base);  in ath79_clocks_init_dt()
660 	iounmap(pll_base);  in ath79_clocks_init_dt()