Lines Matching refs:REG
33 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr)) macro
42 REG(ESR_OFFSET(d->irq - ar7_irq_base))); in ar7_unmask_irq()
48 REG(ECR_OFFSET(d->irq - ar7_irq_base))); in ar7_mask_irq()
54 REG(CR_OFFSET(d->irq - ar7_irq_base))); in ar7_ack_irq()
59 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); in ar7_unmask_sec_irq()
64 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); in ar7_mask_sec_irq()
69 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); in ar7_ack_sec_irq()
98 writel(0xffffffff, REG(ECR_OFFSET(0))); in ar7_irq_init()
99 writel(0xff, REG(ECR_OFFSET(32))); in ar7_irq_init()
100 writel(0xffffffff, REG(SEC_ECR_OFFSET)); in ar7_irq_init()
101 writel(0xffffffff, REG(CR_OFFSET(0))); in ar7_irq_init()
102 writel(0xff, REG(CR_OFFSET(32))); in ar7_irq_init()
103 writel(0xffffffff, REG(SEC_CR_OFFSET)); in ar7_irq_init()
108 writel(i, REG(CHNL_OFFSET(i))); in ar7_irq_init()
136 irq = readl(REG(PIR_OFFSET)) & 0x3f; in ar7_cascade()
143 writel(1, REG(CR_OFFSET(irq))); in ar7_cascade()
144 status = readl(REG(SEC_SR_OFFSET)); in ar7_cascade()