Lines Matching refs:alchemy_rdsys
131 t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f; in alchemy_clk_cpu_recalc()
184 return (alchemy_rdsys(a->reg) & 0xff) * parent_rate; in alchemy_clk_aux_recalc()
268 unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2; in alchemy_clk_setup_sysbus()
490 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_en()
501 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1); in alchemy_clk_fgv1_isen()
512 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_dis()
524 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_setp()
539 return (alchemy_rdsys(c->reg) >> c->shift) & 1; in alchemy_clk_fgv1_getp()
553 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_setr()
566 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2); in alchemy_clk_fgv1_recalc()
592 unsigned long v = alchemy_rdsys(c->reg); in __alchemy_clk_fgv2_en()
617 return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0; in alchemy_clk_fgv2_isen()
626 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_dis()
673 v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */ in alchemy_clk_fgv2_setr()
678 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_setr()
694 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_recalc()
708 if (alchemy_rdsys(c->reg) & (1 << 30)) { in alchemy_clk_fgv2_detr()
789 v = alchemy_rdsys(a->reg); in alchemy_clk_init_fgens()
815 unsigned long v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_isen()
822 unsigned long v = alchemy_rdsys(c->reg); in __alchemy_clk_csrc_en()
849 v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_dis()
881 unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3; in alchemy_clk_csrc_recalc()
910 v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_setr()
1008 v = alchemy_rdsys(a->reg); in alchemy_clk_setup_imux()