Lines Matching refs:r5
85 lwi r5, r1, 0; \
86 mts rmsr, r5; \
90 lwi r5, r1, PT_R5; \
336 swi r5, r1, PT_R5
345 mfs r5, rmsr;
347 swi r5, r1, 0;
354 andi r5, r4, 0x1000; /* Check ESR[DS] */
355 beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
362 andi r5, r4, 0x1F; /* Extract ESR[EXC] */
366 addk r6, r5, r5; /* << 1 */
371 lwi r5, r0, TOPHYS(exception_debug_table)
372 addi r5, r5, 1
373 swi r5, r0, TOPHYS(exception_debug_table)
374 lwi r5, r6, TOPHYS(exception_debug_table)
375 addi r5, r5, 1
376 swi r5, r6, TOPHYS(exception_debug_table)
396 xori r6, r5, 1; /* 00001 = Unaligned Exception */
412 or r5, r1, r0
428 mfs r5, rmsr;
430 ori r5, r5, 2;
431 mts rmsr, r5; /* enable interrupt */
435 mfs r5, rmsr; /* disable interrupt */
437 andi r5, r5, ~2;
438 mts rmsr, r5;
490 lbui r5, r3, 0; /* Exception address in r3 */
493 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
494 lbui r5, r3, 1;
495 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
496 lbui r5, r3, 2;
497 sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
498 lbui r5, r3, 3;
499 sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
504 lbui r5, r3, 0; /* Exception address in r3 */
507 sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
508 lbui r5, r3, 1;
509 sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
514 lbui r5, r0, TOPHYS(ex_reg_op);
517 addk r5, r5, r5;
518 addk r5, r5, r5;
519 addk r5, r5, r5;
520 addk r5, r5, r6;
521 bra r5;
525 lbui r5, r0, TOPHYS(ex_reg_op);
528 add r5, r5, r5;
529 add r5, r5, r5;
530 add r5, r5, r5;
531 add r5, r5, r6;
532 bra r5;
562 lwi r5, r1, 0 /* RMSR */
563 mts rmsr, r5
567 lwi r5, r1, PT_R5
600 ori r5, r0, CONFIG_KERNEL_START
601 cmpu r5, r3, r5
602 bgti r5, ex3
629 bsrli r5, r3, PGDIR_SHIFT - 2
630 andi r5, r5, PAGE_SIZE - 4
632 or r4, r4, r5
634 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
635 beqi r5, ex2 /* Bail if no table */
637 tophys(r5,r5)
640 or r5, r5, r6
641 lwi r4, r5, 0 /* Get Linux PTE */
648 swi r4, r5, 0 /* Update Linux page table */
666 mfs r5, rtlbx /* DEBUG: TBD */
730 bsrli r5, r3, PGDIR_SHIFT - 2
731 andi r5, r5, PAGE_SIZE - 4
733 or r4, r4, r5
735 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
736 beqi r5, ex7 /* Bail if no table */
738 tophys(r5,r5)
741 or r5, r5, r6
742 lwi r4, r5, 0 /* Get Linux PTE */
748 swi r4, r5, 0
801 bsrli r5, r3, PGDIR_SHIFT - 2
802 andi r5, r5, PAGE_SIZE - 4
804 or r4, r4, r5
806 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
807 beqi r5, ex10 /* Bail if no table */
809 tophys(r5,r5)
812 or r5, r5, r6
813 lwi r4, r5, 0 /* Get Linux PTE */
819 swi r4, r5, 0
861 lwi r5, r0, TOPHYS(tlb_index)
862 addik r5, r5, 1 /* MS: inc tlb_index -> use next one */
865 andi r5, r5, MICROBLAZE_TLB_SIZE - 1
867 cmp r31, r5, r6
869 lwi r5, r0, TOPHYS(tlb_skip)
872 swi r5, r0, TOPHYS(tlb_index)
875 mts rtlbx, r5 /* MS: save current TLB */
923 mts rpid, r5 /* Shadow TLBs are automatically */
953 load1: lbui r5, r4, 0; /* Exception address in r4 - delay slot */
956 sbi r5, r6, 0;
957 load2: lbui r5, r4, 1;
958 sbi r5, r6, 1;
959 load3: lbui r5, r4, 2;
960 sbi r5, r6, 2;
961 load4: lbui r5, r4, 3;
962 sbi r5, r6, 3;
970 sbi r5, r6, 0;
971 load5: lbui r5, r4, 1;
972 sbi r5, r6, 1;
976 addik r5, r8, lw_table_vm;
977 bra r5;
982 addik r5, r8, sw_table_vm;
983 bra r5;
985 addik r5, r0, ex_tmp_data_loc_0;
987 swi r3, r5, 0; /* Get the word - delay slot */
989 lbui r3, r5, 0;
991 lbui r3, r5, 1;
993 lbui r3, r5, 2;
995 lbui r3, r5, 3;
1001 lbui r3, r5, 0;
1003 lbui r3, r5, 1;
1007 lbui r3, r5, 2;
1009 lbui r3, r5, 3;
1021 ori r5, r7, 0 /* setup pointer to pt_regs */