Lines Matching full:volatile
17 /* The "volatile" is due to gcc bugs */
18 #define ia64_barrier() asm volatile ("":::"memory")
20 #define ia64_stop() asm volatile (";;"::)
22 #define ia64_invala_gr(regnum) asm volatile ("invala.e r%0" :: "i"(regnum))
24 #define ia64_invala_fr(regnum) asm volatile ("invala.e f%0" :: "i"(regnum))
26 #define ia64_flushrs() asm volatile ("flushrs;;":::"memory")
28 #define ia64_loadrs() asm volatile ("loadrs;;":::"memory")
38 asm volatile ("mov psr.l=%0" :: "r"(val) : "memory"); \
41 asm volatile ("mov ar%0=%1" :: \
46 asm volatile ("mov cr%0=%1" :: \
51 asm volatile ("mov r12=%0" :: \
55 asm volatile ("mov gp=%0" :: "r"(val) : "memory"); \
69 asm volatile ("mov %0=gp" : "=r"(ia64_intri_res)); \
72 asm volatile ("mov %0=ip" : "=r"(ia64_intri_res)); \
75 asm volatile ("mov %0=psr" : "=r"(ia64_intri_res)); \
81 asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res) \
85 asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res) \
89 asm volatile ("mov %0=sp" : "=r" (ia64_intri_res)); \
104 asm volatile ("hint @pause" ::: "memory"); \
172 asm volatile ("ldfs %0=[%1]" :"=f"(__f__): "r"(x)); \
178 asm volatile ("ldfd %0=[%1]" :"=f"(__f__): "r"(x)); \
184 asm volatile ("ldfe %0=[%1]" :"=f"(__f__): "r"(x)); \
190 asm volatile ("ldf8 %0=[%1]" :"=f"(__f__): "r"(x)); \
196 asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \
201 asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \
207 asm volatile ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
213 asm volatile ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
219 asm volatile ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
225 asm volatile ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
231 asm volatile ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
238 asm volatile ("fetchadd4.acq %0=[%1],%2" \
248 asm volatile ("fetchadd4.rel %0=[%1],%2" \
259 asm volatile ("fetchadd8.acq %0=[%1],%2" \
269 asm volatile ("fetchadd8.rel %0=[%1],%2" \
279 asm volatile ("xchg1 %0=[%1],%2" \
287 asm volatile ("xchg2 %0=[%1],%2" : "=r" (ia64_intri_res) \
295 asm volatile ("xchg4 %0=[%1],%2" : "=r" (ia64_intri_res) \
303 asm volatile ("xchg8 %0=[%1],%2" : "=r" (ia64_intri_res) \
311 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
312 asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv": \
320 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
321 asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv": \
329 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
330 asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv": \
338 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
340 asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv": \
348 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
349 asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \
357 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
358 asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv": \
366 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
367 asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv": \
375 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
377 asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv": \
382 #define ia64_mf() asm volatile ("mf" ::: "memory")
383 #define ia64_mfa() asm volatile ("mf.a" ::: "memory")
385 #define ia64_invala() asm volatile ("invala" ::: "memory")
390 asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \
394 #define ia64_srlz_i() asm volatile (";; srlz.i ;;" ::: "memory")
395 #define ia64_srlz_d() asm volatile (";; srlz.d" ::: "memory");
398 # define ia64_dv_serialize_data() asm volatile (".serialize.data");
399 # define ia64_dv_serialize_instruction() asm volatile (".serialize.instruction");
405 #define ia64_nop(x) asm volatile ("nop %0"::"i"(x));
407 #define ia64_itci(addr) asm volatile ("itc.i %0;;" :: "r"(addr) : "memory")
409 #define ia64_itcd(addr) asm volatile ("itc.d %0;;" :: "r"(addr) : "memory")
412 #define ia64_itri(trnum, addr) asm volatile ("itr.i itr[%0]=%1" \
415 #define ia64_itrd(trnum, addr) asm volatile ("itr.d dtr[%0]=%1" \
421 asm volatile ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : "memory"); \
426 asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory")
429 asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory")
432 asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory")
435 asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory")
438 asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory")
441 asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory");
446 asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index)); \
453 asm volatile ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
460 asm volatile ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
467 asm volatile ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
474 asm volatile ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
482 asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
489 asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index)); \
493 #define ia64_native_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory")
496 #define ia64_sync_i() asm volatile (";; sync.i" ::: "memory")
498 #define ia64_native_ssm(mask) asm volatile ("ssm %0":: "i"((mask)) : "memory")
499 #define ia64_native_rsm(mask) asm volatile ("rsm %0":: "i"((mask)) : "memory")
500 #define ia64_sum(mask) asm volatile ("sum %0":: "i"((mask)) : "memory")
501 #define ia64_rum(mask) asm volatile ("rum %0":: "i"((mask)) : "memory")
503 #define ia64_ptce(addr) asm volatile ("ptc.e %0" :: "r"(addr))
507 asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory"); \
513 asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory"); \
518 asm volatile ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory")
521 asm volatile ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory")
526 asm volatile ("ttag %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \
542 asm volatile ("lfetch [%0]" : : "r"(y)); \
545 asm volatile ("lfetch.nt1 [%0]" : : "r"(y)); \
548 asm volatile ("lfetch.nt2 [%0]" : : "r"(y)); \
551 asm volatile ("lfetch.nta [%0]" : : "r"(y)); \
560 asm volatile ("lfetch.excl [%0]" :: "r"(y)); \
563 asm volatile ("lfetch.excl.nt1 [%0]" :: "r"(y)); \
566 asm volatile ("lfetch.excl.nt2 [%0]" :: "r"(y)); \
569 asm volatile ("lfetch.excl.nta [%0]" :: "r"(y)); \
578 asm volatile ("lfetch.fault [%0]" : : "r"(y)); \
581 asm volatile ("lfetch.fault.nt1 [%0]" : : "r"(y)); \
584 asm volatile ("lfetch.fault.nt2 [%0]" : : "r"(y)); \
587 asm volatile ("lfetch.fault.nta [%0]" : : "r"(y)); \
596 asm volatile ("lfetch.fault.excl [%0]" :: "r"(y)); \
599 asm volatile ("lfetch.fault.excl.nt1 [%0]" :: "r"(y)); \
602 asm volatile ("lfetch.fault.excl.nt2 [%0]" :: "r"(y)); \
605 asm volatile ("lfetch.fault.excl.nta [%0]" :: "r"(y)); \
612 asm volatile (";; cmp.ne p6,p7=%0,r0;;" \