Lines Matching refs:x20
160 stp x20, x21, [sp, #16 * 10]
169 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
171 disable_step_tsk x19, x20 // exceptions when scheduling.
179 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
180 str x20, [sp, #S_ORIG_ADDR_LIMIT]
181 mov x20, #USER_DS
182 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
243 mrs_s x20, SYS_ICC_PMR_EL1
244 str x20, [sp, #S_PMR_SAVE]
262 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
263 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
270 ldr x20, [sp, #S_PMR_SAVE]
271 msr_s SYS_ICC_PMR_EL1, x20
359 ldp x20, x21, [sp, #16 * 10]
656 gic_prio_irq_setup pmr=x20, tmp=x1
660 test_irqs_unmasked res=x0, pmr=x20
693 test_irqs_unmasked res=x0, pmr=x20
701 test_irqs_unmasked res=x0, pmr=x20
929 gic_prio_irq_setup pmr=x20, tmp=x0
1141 stp x19, x20, [x8], #16 // store callee-saved registers
1149 ldp x19, x20, [x8], #16 // restore callee-saved registers
1168 mov x0, x20
1275 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]