Lines Matching +full:interrupt +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53";
27 enable-method = "psci";
28 operating-points-v2 = <&cpu_opp_table>;
30 cpu-idle-states = <&CPU_SLEEP_0>;
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
38 operating-points-v2 = <&cpu_opp_table>;
39 cpu-idle-states = <&CPU_SLEEP_0>;
43 compatible = "arm,cortex-a53";
45 enable-method = "psci";
47 operating-points-v2 = <&cpu_opp_table>;
48 cpu-idle-states = <&CPU_SLEEP_0>;
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-idle-states = <&CPU_SLEEP_0>;
60 idle-states {
61 entry-method = "psci";
63 CPU_SLEEP_0: cpu-sleep-0 {
64 compatible = "arm,idle-state";
65 arm,psci-suspend-param = <0x40000000>;
66 local-timer-stop;
67 entry-latency-us = <300>;
68 exit-latency-us = <600>;
69 min-residency-us = <10000>;
74 cpu_opp_table: cpu-opp-table {
75 compatible = "operating-points-v2";
76 opp-shared;
78 opp-hz = /bits/ 64 <1199999988>;
79 opp-microvolt = <1000000>;
80 clock-latency-ns = <500000>;
83 opp-hz = /bits/ 64 <599999994>;
84 opp-microvolt = <1000000>;
85 clock-latency-ns = <500000>;
88 opp-hz = /bits/ 64 <399999996>;
89 opp-microvolt = <1000000>;
90 clock-latency-ns = <500000>;
93 opp-hz = /bits/ 64 <299999997>;
94 opp-microvolt = <1000000>;
95 clock-latency-ns = <500000>;
105 compatible = "arm,armv8-pmuv3";
106 interrupt-parent = <&gic>;
114 compatible = "arm,psci-0.2";
119 compatible = "arm,armv8-timer";
120 interrupt-parent = <&gic>;
127 amba_apu: amba-apu@0 {
128 compatible = "simple-bus";
129 #address-cells = <2>;
130 #size-cells = <1>;
133 gic: interrupt-controller@f9010000 {
134 compatible = "arm,gic-400", "arm,cortex-a15-gic";
135 #interrupt-cells = <3>;
140 interrupt-controller;
141 interrupt-parent = <&gic>;
147 compatible = "simple-bus";
148 #address-cells = <2>;
149 #size-cells = <2>;
153 compatible = "xlnx,zynq-can-1.0";
155 clock-names = "can_clk", "pclk";
158 interrupt-parent = <&gic>;
159 tx-fifo-depth = <0x40>;
160 rx-fifo-depth = <0x40>;
164 compatible = "xlnx,zynq-can-1.0";
166 clock-names = "can_clk", "pclk";
169 interrupt-parent = <&gic>;
170 tx-fifo-depth = <0x40>;
171 rx-fifo-depth = <0x40>;
175 compatible = "arm,cci-400";
178 #address-cells = <1>;
179 #size-cells = <1>;
182 compatible = "arm,cci-400-pmu,r1";
184 interrupt-parent = <&gic>;
196 compatible = "xlnx,zynqmp-dma-1.0";
198 interrupt-parent = <&gic>;
200 clock-names = "clk_main", "clk_apb";
201 xlnx,bus-width = <128>;
206 compatible = "xlnx,zynqmp-dma-1.0";
208 interrupt-parent = <&gic>;
210 clock-names = "clk_main", "clk_apb";
211 xlnx,bus-width = <128>;
216 compatible = "xlnx,zynqmp-dma-1.0";
218 interrupt-parent = <&gic>;
220 clock-names = "clk_main", "clk_apb";
221 xlnx,bus-width = <128>;
226 compatible = "xlnx,zynqmp-dma-1.0";
228 interrupt-parent = <&gic>;
230 clock-names = "clk_main", "clk_apb";
231 xlnx,bus-width = <128>;
236 compatible = "xlnx,zynqmp-dma-1.0";
238 interrupt-parent = <&gic>;
240 clock-names = "clk_main", "clk_apb";
241 xlnx,bus-width = <128>;
246 compatible = "xlnx,zynqmp-dma-1.0";
248 interrupt-parent = <&gic>;
250 clock-names = "clk_main", "clk_apb";
251 xlnx,bus-width = <128>;
256 compatible = "xlnx,zynqmp-dma-1.0";
258 interrupt-parent = <&gic>;
260 clock-names = "clk_main", "clk_apb";
261 xlnx,bus-width = <128>;
266 compatible = "xlnx,zynqmp-dma-1.0";
268 interrupt-parent = <&gic>;
270 clock-names = "clk_main", "clk_apb";
271 xlnx,bus-width = <128>;
280 compatible = "xlnx,zynqmp-dma-1.0";
282 interrupt-parent = <&gic>;
284 clock-names = "clk_main", "clk_apb";
285 xlnx,bus-width = <64>;
290 compatible = "xlnx,zynqmp-dma-1.0";
292 interrupt-parent = <&gic>;
294 clock-names = "clk_main", "clk_apb";
295 xlnx,bus-width = <64>;
300 compatible = "xlnx,zynqmp-dma-1.0";
302 interrupt-parent = <&gic>;
304 clock-names = "clk_main", "clk_apb";
305 xlnx,bus-width = <64>;
310 compatible = "xlnx,zynqmp-dma-1.0";
312 interrupt-parent = <&gic>;
314 clock-names = "clk_main", "clk_apb";
315 xlnx,bus-width = <64>;
320 compatible = "xlnx,zynqmp-dma-1.0";
322 interrupt-parent = <&gic>;
324 clock-names = "clk_main", "clk_apb";
325 xlnx,bus-width = <64>;
330 compatible = "xlnx,zynqmp-dma-1.0";
332 interrupt-parent = <&gic>;
334 clock-names = "clk_main", "clk_apb";
335 xlnx,bus-width = <64>;
340 compatible = "xlnx,zynqmp-dma-1.0";
342 interrupt-parent = <&gic>;
344 clock-names = "clk_main", "clk_apb";
345 xlnx,bus-width = <64>;
350 compatible = "xlnx,zynqmp-dma-1.0";
352 interrupt-parent = <&gic>;
354 clock-names = "clk_main", "clk_apb";
355 xlnx,bus-width = <64>;
358 mc: memory-controller@fd070000 {
359 compatible = "xlnx,zynqmp-ddrc-2.40a";
361 interrupt-parent = <&gic>;
366 compatible = "cdns,zynqmp-gem", "cdns,gem";
368 interrupt-parent = <&gic>;
371 clock-names = "pclk", "hclk", "tx_clk";
372 #address-cells = <1>;
373 #size-cells = <0>;
377 compatible = "cdns,zynqmp-gem", "cdns,gem";
379 interrupt-parent = <&gic>;
382 clock-names = "pclk", "hclk", "tx_clk";
383 #address-cells = <1>;
384 #size-cells = <0>;
388 compatible = "cdns,zynqmp-gem", "cdns,gem";
390 interrupt-parent = <&gic>;
393 clock-names = "pclk", "hclk", "tx_clk";
394 #address-cells = <1>;
395 #size-cells = <0>;
399 compatible = "cdns,zynqmp-gem", "cdns,gem";
401 interrupt-parent = <&gic>;
404 clock-names = "pclk", "hclk", "tx_clk";
405 #address-cells = <1>;
406 #size-cells = <0>;
410 compatible = "xlnx,zynqmp-gpio-1.0";
412 #gpio-cells = <0x2>;
413 gpio-controller;
414 interrupt-parent = <&gic>;
416 interrupt-controller;
417 #interrupt-cells = <2>;
422 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
424 interrupt-parent = <&gic>;
427 #address-cells = <1>;
428 #size-cells = <0>;
432 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
434 interrupt-parent = <&gic>;
437 #address-cells = <1>;
438 #size-cells = <0>;
442 compatible = "xlnx,nwl-pcie-2.11";
444 #address-cells = <3>;
445 #size-cells = <2>;
446 #interrupt-cells = <1>;
447 msi-controller;
449 interrupt-parent = <&gic>;
455 interrupt-names = "misc", "dummy", "intx",
457 msi-parent = <&pcie>;
461 reg-names = "breg", "pcireg", "cfg";
462 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-pref…
464 bus-range = <0x00 0xff>;
465 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
466 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
470 pcie_intc: legacy-interrupt-controller {
471 interrupt-controller;
472 #address-cells = <0>;
473 #interrupt-cells = <1>;
478 compatible = "xlnx,zynqmp-rtc";
481 interrupt-parent = <&gic>;
483 interrupt-names = "alarm", "sec";
488 compatible = "ceva,ahci-1v84";
491 interrupt-parent = <&gic>;
496 compatible = "arasan,sdhci-8.9a";
498 interrupt-parent = <&gic>;
501 clock-names = "clk_xin", "clk_ahb";
505 compatible = "arasan,sdhci-8.9a";
507 interrupt-parent = <&gic>;
510 clock-names = "clk_xin", "clk_ahb";
514 compatible = "arm,mmu-500";
517 #global-interrupts = <1>;
518 interrupt-parent = <&gic>;
527 compatible = "cdns,spi-r1p6";
529 interrupt-parent = <&gic>;
532 clock-names = "ref_clk", "pclk";
533 #address-cells = <1>;
534 #size-cells = <0>;
538 compatible = "cdns,spi-r1p6";
540 interrupt-parent = <&gic>;
543 clock-names = "ref_clk", "pclk";
544 #address-cells = <1>;
545 #size-cells = <0>;
551 interrupt-parent = <&gic>;
554 timer-width = <32>;
560 interrupt-parent = <&gic>;
563 timer-width = <32>;
569 interrupt-parent = <&gic>;
572 timer-width = <32>;
578 interrupt-parent = <&gic>;
581 timer-width = <32>;
585 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
587 interrupt-parent = <&gic>;
590 clock-names = "uart_clk", "pclk";
594 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
596 interrupt-parent = <&gic>;
599 clock-names = "uart_clk", "pclk";
605 interrupt-parent = <&gic>;
608 clock-names = "clk_xin", "clk_ahb";
614 interrupt-parent = <&gic>;
617 clock-names = "clk_xin", "clk_ahb";
621 compatible = "cdns,wdt-r1p2";
623 interrupt-parent = <&gic>;
626 timeout-sec = <10>;