Lines Matching +full:clock +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0+
3 * Clock specification for Xilinx ZynqMP
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <100000000>;
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <125000000>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <200000000>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <250000000>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <300000000>;
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <600000000>;
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <100000000>;
51 clock-accuracy = <100>;
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <24576000>;
58 clock-accuracy = <100>;
61 dpdma_clk: dpdma-clk {
62 compatible = "fixed-clock";
63 #clock-cells = <0x0>;
64 clock-frequency = <533000000>;
67 drm_clock: drm-clock {
68 compatible = "fixed-clock";
69 #clock-cells = <0x0>;
70 clock-frequency = <262750000>;
71 clock-accuracy = <0x64>;