Lines Matching +full:psci +full:- +full:0
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
20 psci {
21 compatible = "arm,psci-1.0", "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu0: cpu@0 {
30 compatible = "arm,cortex-a53";
32 reg = <0x0>;
33 enable-method = "psci";
34 next-level-cache = <&l2>;
35 cpu-idle-states = <&CPU_SLEEP_0>;
39 compatible = "arm,cortex-a53";
41 reg = <0x1>;
42 enable-method = "psci";
43 next-level-cache = <&l2>;
44 cpu-idle-states = <&CPU_SLEEP_0>;
48 compatible = "arm,cortex-a53";
50 reg = <0x2>;
51 enable-method = "psci";
52 next-level-cache = <&l2>;
53 cpu-idle-states = <&CPU_SLEEP_0>;
57 compatible = "arm,cortex-a53";
59 reg = <0x3>;
60 enable-method = "psci";
61 next-level-cache = <&l2>;
62 cpu-idle-states = <&CPU_SLEEP_0>;
69 idle-states {
70 entry-method = "psci";
71 CPU_SLEEP_0: cpu-sleep-0 {
72 compatible = "arm,idle-state";
73 local-timer-stop;
74 arm,psci-suspend-param = <0x0010000>;
75 entry-latency-us = <75>;
76 exit-latency-us = <155>;
77 min-residency-us = <1000>;
83 compatible = "fixed-clock";
84 #clock-cells = <0>;
85 clock-frequency = <25000000>;
89 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
94 interrupt-affinity = <&cpu0>,
101 compatible = "arm,armv8-timer";
109 compatible = "simple-bus";
110 #address-cells = <1>;
111 #size-cells = <1>;
112 ranges = <0 0 0xf7000000 0x1000000>;
114 gic: interrupt-controller@901000 {
115 compatible = "arm,gic-400";
116 #interrupt-cells = <3>;
117 interrupt-controller;
118 reg = <0x901000 0x1000>,
119 <0x902000 0x2000>,
120 <0x904000 0x2000>,
121 <0x906000 0x2000>;
126 compatible = "simple-bus";
127 #address-cells = <1>;
128 #size-cells = <1>;
130 ranges = <0 0xe80000 0x10000>;
131 interrupt-parent = <&aic>;
134 compatible = "snps,dw-apb-gpio";
135 reg = <0x0400 0x400>;
136 #address-cells = <1>;
137 #size-cells = <0>;
139 porta: gpio-port@0 {
140 compatible = "snps,dw-apb-gpio-port";
141 gpio-controller;
142 #gpio-cells = <2>;
143 snps,nr-gpios = <32>;
144 reg = <0>;
145 interrupt-controller;
146 #interrupt-cells = <2>;
147 interrupts = <0>;
152 compatible = "snps,dw-apb-gpio";
153 reg = <0x0800 0x400>;
154 #address-cells = <1>;
155 #size-cells = <0>;
157 portb: gpio-port@1 {
158 compatible = "snps,dw-apb-gpio-port";
159 gpio-controller;
160 #gpio-cells = <2>;
161 snps,nr-gpios = <32>;
162 reg = <0>;
163 interrupt-controller;
164 #interrupt-cells = <2>;
170 compatible = "snps,dw-apb-gpio";
171 reg = <0x0c00 0x400>;
172 #address-cells = <1>;
173 #size-cells = <0>;
175 portc: gpio-port@2 {
176 compatible = "snps,dw-apb-gpio-port";
177 gpio-controller;
178 #gpio-cells = <2>;
179 snps,nr-gpios = <32>;
180 reg = <0>;
181 interrupt-controller;
182 #interrupt-cells = <2>;
188 compatible = "snps,dw-apb-gpio";
189 reg = <0x1000 0x400>;
190 #address-cells = <1>;
191 #size-cells = <0>;
193 portd: gpio-port@3 {
194 compatible = "snps,dw-apb-gpio-port";
195 gpio-controller;
196 #gpio-cells = <2>;
197 snps,nr-gpios = <32>;
198 reg = <0>;
199 interrupt-controller;
200 #interrupt-cells = <2>;
205 aic: interrupt-controller@3800 {
206 compatible = "snps,dw-apb-ictl";
207 reg = <0x3800 0x30>;
208 interrupt-controller;
209 #interrupt-cells = <1>;
210 interrupt-parent = <&gic>;
215 soc_pinctrl: pin-controller@ea8000 {
216 compatible = "marvell,berlin4ct-soc-pinctrl";
217 reg = <0xea8000 0x14>;
220 avio_pinctrl: pin-controller@ea8400 {
221 compatible = "marvell,berlin4ct-avio-pinctrl";
222 reg = <0xea8400 0x8>;
226 compatible = "simple-bus";
227 #address-cells = <1>;
228 #size-cells = <1>;
229 ranges = <0 0xfc0000 0x10000>;
230 interrupt-parent = <&sic>;
232 sic: interrupt-controller@1000 {
233 compatible = "snps,dw-apb-ictl";
234 reg = <0x1000 0x30>;
235 interrupt-controller;
236 #interrupt-cells = <1>;
237 interrupt-parent = <&gic>;
242 compatible = "snps,dw-wdt";
243 reg = <0x3000 0x100>;
245 interrupts = <0>;
249 compatible = "snps,dw-wdt";
250 reg = <0x4000 0x100>;
256 compatible = "snps,dw-wdt";
257 reg = <0x5000 0x100>;
263 compatible = "snps,dw-apb-gpio";
264 reg = <0x8000 0x400>;
265 #address-cells = <1>;
266 #size-cells = <0>;
268 porte: gpio-port@4 {
269 compatible = "snps,dw-apb-gpio-port";
270 gpio-controller;
271 #gpio-cells = <2>;
272 snps,nr-gpios = <32>;
273 reg = <0>;
278 compatible = "snps,dw-apb-gpio";
279 reg = <0x9000 0x400>;
280 #address-cells = <1>;
281 #size-cells = <0>;
283 portf: gpio-port@5 {
284 compatible = "snps,dw-apb-gpio-port";
285 gpio-controller;
286 #gpio-cells = <2>;
287 snps,nr-gpios = <32>;
288 reg = <0>;
293 compatible = "snps,dw-apb-uart";
294 reg = <0xd000 0x100>;
297 reg-shift = <2>;
299 pinctrl-0 = <&uart0_pmux>;
300 pinctrl-names = "default";
304 system_pinctrl: pin-controller@fe2200 {
305 compatible = "marvell,berlin4ct-system-pinctrl";
306 reg = <0xfe2200 0xc>;
308 uart0_pmux: uart0-pmux {