Lines Matching +full:nvmem +full:- +full:cells +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
12 compatible = "socionext,uniphier-pxs3";
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <0>;
21 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 operating-points-v2 = <&cluster0_opp>;
49 compatible = "arm,cortex-a53";
52 enable-method = "psci";
53 operating-points-v2 = <&cluster0_opp>;
58 compatible = "arm,cortex-a53";
61 enable-method = "psci";
62 operating-points-v2 = <&cluster0_opp>;
67 compatible = "arm,cortex-a53";
70 enable-method = "psci";
71 operating-points-v2 = <&cluster0_opp>;
75 cluster0_opp: opp-table {
76 compatible = "operating-points-v2";
77 opp-shared;
79 opp-250000000 {
80 opp-hz = /bits/ 64 <250000000>;
81 clock-latency-ns = <300>;
83 opp-325000000 {
84 opp-hz = /bits/ 64 <325000000>;
85 clock-latency-ns = <300>;
87 opp-500000000 {
88 opp-hz = /bits/ 64 <500000000>;
89 clock-latency-ns = <300>;
91 opp-650000000 {
92 opp-hz = /bits/ 64 <650000000>;
93 clock-latency-ns = <300>;
95 opp-666667000 {
96 opp-hz = /bits/ 64 <666667000>;
97 clock-latency-ns = <300>;
99 opp-866667000 {
100 opp-hz = /bits/ 64 <866667000>;
101 clock-latency-ns = <300>;
103 opp-1000000000 {
104 opp-hz = /bits/ 64 <1000000000>;
105 clock-latency-ns = <300>;
107 opp-1300000000 {
108 opp-hz = /bits/ 64 <1300000000>;
109 clock-latency-ns = <300>;
114 compatible = "arm,psci-1.0";
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <25000000>;
126 emmc_pwrseq: emmc-pwrseq {
127 compatible = "mmc-pwrseq-emmc";
128 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
132 compatible = "arm,armv8-timer";
139 reserved-memory {
140 #address-cells = <2>;
141 #size-cells = <2>;
144 secure-memory@81000000 {
146 no-map;
151 compatible = "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
157 compatible = "socionext,uniphier-scssi";
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_spi0>;
168 compatible = "socionext,uniphier-scssi";
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_spi1>;
179 compatible = "socionext,uniphier-uart";
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_uart0>;
190 compatible = "socionext,uniphier-uart";
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_uart1>;
201 compatible = "socionext,uniphier-uart";
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_uart2>;
212 compatible = "socionext,uniphier-uart";
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_uart3>;
223 compatible = "socionext,uniphier-gpio";
225 interrupt-parent = <&aidet>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 gpio-controller;
229 #gpio-cells = <2>;
230 gpio-ranges = <&pinctrl 0 0 0>,
233 gpio-ranges-group-names = "gpio_range0",
237 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
242 compatible = "socionext,uniphier-fi2c";
245 #address-cells = <1>;
246 #size-cells = <0>;
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_i2c0>;
252 clock-frequency = <100000>;
256 compatible = "socionext,uniphier-fi2c";
259 #address-cells = <1>;
260 #size-cells = <0>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_i2c1>;
266 clock-frequency = <100000>;
270 compatible = "socionext,uniphier-fi2c";
273 #address-cells = <1>;
274 #size-cells = <0>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_i2c2>;
280 clock-frequency = <100000>;
284 compatible = "socionext,uniphier-fi2c";
287 #address-cells = <1>;
288 #size-cells = <0>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_i2c3>;
294 clock-frequency = <100000>;
297 /* chip-internal connection for HDMI */
299 compatible = "socionext,uniphier-fi2c";
301 #address-cells = <1>;
302 #size-cells = <0>;
306 clock-frequency = <400000>;
309 system_bus: system-bus@58c00000 {
310 compatible = "socionext,uniphier-system-bus";
313 #address-cells = <2>;
314 #size-cells = <1>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_system_bus>;
320 compatible = "socionext,uniphier-smpctrl";
325 compatible = "socionext,uniphier-pxs3-sdctrl",
326 "simple-mfd", "syscon";
330 compatible = "socionext,uniphier-pxs3-sd-clock";
331 #clock-cells = <1>;
335 compatible = "socionext,uniphier-pxs3-sd-reset";
336 #reset-cells = <1>;
341 compatible = "socionext,uniphier-pxs3-perictrl",
342 "simple-mfd", "syscon";
346 compatible = "socionext,uniphier-pxs3-peri-clock";
347 #clock-cells = <1>;
351 compatible = "socionext,uniphier-pxs3-peri-reset";
352 #reset-cells = <1>;
357 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_emmc>;
364 bus-width = <8>;
365 mmc-ddr-1_8v;
366 mmc-hs200-1_8v;
367 mmc-pwrseq = <&emmc_pwrseq>;
368 cdns,phy-input-delay-legacy = <9>;
369 cdns,phy-input-delay-mmc-highspeed = <2>;
370 cdns,phy-input-delay-mmc-ddr = <3>;
371 cdns,phy-dll-delay-sdclk = <21>;
372 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
376 compatible = "socionext,uniphier-sd-v3.1.1";
380 pinctrl-names = "default", "uhs";
381 pinctrl-0 = <&pinctrl_sd>;
382 pinctrl-1 = <&pinctrl_sd_uhs>;
384 reset-names = "host";
386 bus-width = <4>;
387 cap-sd-highspeed;
388 sd-uhs-sdr12;
389 sd-uhs-sdr25;
390 sd-uhs-sdr50;
393 soc_glue: soc-glue@5f800000 {
394 compatible = "socionext,uniphier-pxs3-soc-glue",
395 "simple-mfd", "syscon";
399 compatible = "socionext,uniphier-pxs3-pinctrl";
403 soc-glue@5f900000 {
404 compatible = "socionext,uniphier-pxs3-soc-glue-debug",
405 "simple-mfd";
406 #address-cells = <1>;
407 #size-cells = <1>;
411 compatible = "socionext,uniphier-efuse";
416 compatible = "socionext,uniphier-efuse";
418 #address-cells = <1>;
419 #size-cells = <1>;
421 /* USB cells */
466 compatible = "socionext,uniphier-pxs3-aidet";
468 interrupt-controller;
469 #interrupt-cells = <2>;
472 gic: interrupt-controller@5fe00000 {
473 compatible = "arm,gic-v3";
476 interrupt-controller;
477 #interrupt-cells = <3>;
482 compatible = "socionext,uniphier-pxs3-sysctrl",
483 "simple-mfd", "syscon";
487 compatible = "socionext,uniphier-pxs3-clock";
488 #clock-cells = <1>;
492 compatible = "socionext,uniphier-pxs3-reset";
493 #reset-cells = <1>;
497 compatible = "socionext,uniphier-wdt";
502 compatible = "socionext,uniphier-pxs3-ave4";
506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_ether_rgmii>;
508 clock-names = "ether";
510 reset-names = "ether";
512 phy-mode = "rgmii";
513 local-mac-address = [00 00 00 00 00 00];
514 socionext,syscon-phy-mode = <&soc_glue 0>;
517 #address-cells = <1>;
518 #size-cells = <0>;
523 compatible = "socionext,uniphier-pxs3-ave4";
527 pinctrl-names = "default";
528 pinctrl-0 = <&pinctrl_ether1_rgmii>;
529 clock-names = "ether";
531 reset-names = "ether";
533 phy-mode = "rgmii";
534 local-mac-address = [00 00 00 00 00 00];
535 socionext,syscon-phy-mode = <&soc_glue 1>;
538 #address-cells = <1>;
539 #size-cells = <0>;
544 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
547 interrupt-names = "host", "peripheral";
549 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
551 clock-names = "ref", "bus_early", "suspend";
559 usb-glue@65b00000 {
560 compatible = "socionext,uniphier-pxs3-dwc3-glue",
561 "simple-mfd";
562 #address-cells = <1>;
563 #size-cells = <1>;
567 compatible = "socionext,uniphier-pxs3-usb3-reset";
569 #reset-cells = <1>;
570 clock-names = "link";
572 reset-names = "link";
577 compatible = "socionext,uniphier-pxs3-usb3-regulator";
579 clock-names = "link";
581 reset-names = "link";
586 compatible = "socionext,uniphier-pxs3-usb3-regulator";
588 clock-names = "link";
590 reset-names = "link";
594 usb0_hsphy0: hs-phy@200 {
595 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
597 #phy-cells = <0>;
598 clock-names = "link", "phy";
600 reset-names = "link", "phy";
602 vbus-supply = <&usb0_vbus0>;
603 nvmem-cell-names = "rterm", "sel_t", "hs_i";
604 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
608 usb0_hsphy1: hs-phy@210 {
609 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
611 #phy-cells = <0>;
612 clock-names = "link", "phy";
614 reset-names = "link", "phy";
616 vbus-supply = <&usb0_vbus1>;
617 nvmem-cell-names = "rterm", "sel_t", "hs_i";
618 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
622 usb0_ssphy0: ss-phy@300 {
623 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
625 #phy-cells = <0>;
626 clock-names = "link", "phy";
628 reset-names = "link", "phy";
630 vbus-supply = <&usb0_vbus0>;
633 usb0_ssphy1: ss-phy@310 {
634 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
636 #phy-cells = <0>;
637 clock-names = "link", "phy";
639 reset-names = "link", "phy";
641 vbus-supply = <&usb0_vbus1>;
646 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
649 interrupt-names = "host", "peripheral";
651 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
653 clock-names = "ref", "bus_early", "suspend";
661 usb-glue@65d00000 {
662 compatible = "socionext,uniphier-pxs3-dwc3-glue",
663 "simple-mfd";
664 #address-cells = <1>;
665 #size-cells = <1>;
669 compatible = "socionext,uniphier-pxs3-usb3-reset";
671 #reset-cells = <1>;
672 clock-names = "link";
674 reset-names = "link";
679 compatible = "socionext,uniphier-pxs3-usb3-regulator";
681 clock-names = "link";
683 reset-names = "link";
688 compatible = "socionext,uniphier-pxs3-usb3-regulator";
690 clock-names = "link";
692 reset-names = "link";
696 usb1_hsphy0: hs-phy@200 {
697 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
699 #phy-cells = <0>;
700 clock-names = "link", "phy", "phy-ext";
703 reset-names = "link", "phy";
705 vbus-supply = <&usb1_vbus0>;
706 nvmem-cell-names = "rterm", "sel_t", "hs_i";
707 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
711 usb1_hsphy1: hs-phy@210 {
712 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
714 #phy-cells = <0>;
715 clock-names = "link", "phy", "phy-ext";
718 reset-names = "link", "phy";
720 vbus-supply = <&usb1_vbus1>;
721 nvmem-cell-names = "rterm", "sel_t", "hs_i";
722 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
726 usb1_ssphy0: ss-phy@300 {
727 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
729 #phy-cells = <0>;
730 clock-names = "link", "phy", "phy-ext";
733 reset-names = "link", "phy";
735 vbus-supply = <&usb1_vbus0>;
740 compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
742 reg-names = "dbi", "link", "config";
745 #address-cells = <3>;
746 #size-cells = <2>;
749 num-lanes = <1>;
750 num-viewport = <1>;
751 bus-range = <0x0 0xff>;
756 /* non-prefetchable memory */
758 #interrupt-cells = <1>;
759 interrupt-names = "dma", "msi";
761 interrupt-map-mask = <0 0 0 7>;
762 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
766 phy-names = "pcie-phy";
769 pcie_intc: legacy-interrupt-controller {
770 interrupt-controller;
771 #interrupt-cells = <1>;
772 interrupt-parent = <&gic>;
778 compatible = "socionext,uniphier-pxs3-pcie-phy";
780 #phy-cells = <0>;
787 compatible = "socionext,uniphier-denali-nand-v5b";
789 reg-names = "nand_data", "denali_reg";
791 #address-cells = <1>;
792 #size-cells = <0>;
794 pinctrl-names = "default";
795 pinctrl-0 = <&pinctrl_nand>;
796 clock-names = "nand", "nand_x", "ecc";
803 #include "uniphier-pinctrl.dtsi"