Lines Matching +full:nvmem +full:- +full:cells +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-ld20";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
44 compatible = "arm,cortex-a72";
47 enable-method = "psci";
48 operating-points-v2 = <&cluster0_opp>;
49 #cooling-cells = <2>;
54 compatible = "arm,cortex-a72";
57 enable-method = "psci";
58 operating-points-v2 = <&cluster0_opp>;
59 #cooling-cells = <2>;
64 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 operating-points-v2 = <&cluster1_opp>;
69 #cooling-cells = <2>;
74 compatible = "arm,cortex-a53";
77 enable-method = "psci";
78 operating-points-v2 = <&cluster1_opp>;
79 #cooling-cells = <2>;
83 cluster0_opp: opp-table0 {
84 compatible = "operating-points-v2";
85 opp-shared;
87 opp-250000000 {
88 opp-hz = /bits/ 64 <250000000>;
89 clock-latency-ns = <300>;
91 opp-275000000 {
92 opp-hz = /bits/ 64 <275000000>;
93 clock-latency-ns = <300>;
95 opp-500000000 {
96 opp-hz = /bits/ 64 <500000000>;
97 clock-latency-ns = <300>;
99 opp-550000000 {
100 opp-hz = /bits/ 64 <550000000>;
101 clock-latency-ns = <300>;
103 opp-666667000 {
104 opp-hz = /bits/ 64 <666667000>;
105 clock-latency-ns = <300>;
107 opp-733334000 {
108 opp-hz = /bits/ 64 <733334000>;
109 clock-latency-ns = <300>;
111 opp-1000000000 {
112 opp-hz = /bits/ 64 <1000000000>;
113 clock-latency-ns = <300>;
115 opp-1100000000 {
116 opp-hz = /bits/ 64 <1100000000>;
117 clock-latency-ns = <300>;
121 cluster1_opp: opp-table1 {
122 compatible = "operating-points-v2";
123 opp-shared;
125 opp-250000000 {
126 opp-hz = /bits/ 64 <250000000>;
127 clock-latency-ns = <300>;
129 opp-275000000 {
130 opp-hz = /bits/ 64 <275000000>;
131 clock-latency-ns = <300>;
133 opp-500000000 {
134 opp-hz = /bits/ 64 <500000000>;
135 clock-latency-ns = <300>;
137 opp-550000000 {
138 opp-hz = /bits/ 64 <550000000>;
139 clock-latency-ns = <300>;
141 opp-666667000 {
142 opp-hz = /bits/ 64 <666667000>;
143 clock-latency-ns = <300>;
145 opp-733334000 {
146 opp-hz = /bits/ 64 <733334000>;
147 clock-latency-ns = <300>;
149 opp-1000000000 {
150 opp-hz = /bits/ 64 <1000000000>;
151 clock-latency-ns = <300>;
153 opp-1100000000 {
154 opp-hz = /bits/ 64 <1100000000>;
155 clock-latency-ns = <300>;
160 compatible = "arm,psci-1.0";
166 compatible = "fixed-clock";
167 #clock-cells = <0>;
168 clock-frequency = <25000000>;
172 emmc_pwrseq: emmc-pwrseq {
173 compatible = "mmc-pwrseq-emmc";
174 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
178 compatible = "arm,armv8-timer";
185 thermal-zones {
186 cpu-thermal {
187 polling-delay-passive = <250>; /* 250ms */
188 polling-delay = <1000>; /* 1000ms */
189 thermal-sensors = <&pvtctl>;
192 cpu_crit: cpu-crit {
197 cpu_alert: cpu-alert {
204 cooling-maps {
207 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
216 reserved-memory {
217 #address-cells = <2>;
218 #size-cells = <2>;
221 secure-memory@81000000 {
223 no-map;
228 compatible = "simple-bus";
229 #address-cells = <1>;
230 #size-cells = <1>;
234 compatible = "socionext,uniphier-scssi";
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_spi0>;
245 compatible = "socionext,uniphier-scssi";
249 pinctrl-names = "default";
250 pinctrl-0 = <&pinctrl_spi1>;
256 compatible = "socionext,uniphier-scssi";
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_spi2>;
267 compatible = "socionext,uniphier-scssi";
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_spi3>;
278 compatible = "socionext,uniphier-uart";
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_uart0>;
289 compatible = "socionext,uniphier-uart";
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_uart1>;
300 compatible = "socionext,uniphier-uart";
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_uart2>;
311 compatible = "socionext,uniphier-uart";
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_uart3>;
322 compatible = "socionext,uniphier-gpio";
324 interrupt-parent = <&aidet>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 gpio-controller;
328 #gpio-cells = <2>;
329 gpio-ranges = <&pinctrl 0 0 0>,
332 gpio-ranges-group-names = "gpio_range0",
336 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
341 compatible = "socionext,uniphier-ld20-aio";
344 pinctrl-names = "default";
345 pinctrl-0 = <&pinctrl_aout1>,
347 clock-names = "aio";
349 reset-names = "aio";
351 #sound-dai-cells = <1>;
366 dai-format = "i2s";
367 remote-endpoint = <&evea_line>;
378 dai-format = "i2s";
379 remote-endpoint = <&evea_hp>;
405 compatible = "socionext,uniphier-evea";
407 clock-names = "evea", "exiv";
409 reset-names = "evea", "exiv", "adamv";
411 #sound-dai-cells = <1>;
415 remote-endpoint = <&i2s_line>;
421 remote-endpoint = <&i2s_hp>;
427 compatible = "socionext,uniphier-ld20-adamv",
428 "simple-mfd", "syscon";
432 compatible = "socionext,uniphier-ld20-adamv-reset";
433 #reset-cells = <1>;
438 compatible = "socionext,uniphier-fi2c";
441 #address-cells = <1>;
442 #size-cells = <0>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&pinctrl_i2c0>;
448 clock-frequency = <100000>;
452 compatible = "socionext,uniphier-fi2c";
455 #address-cells = <1>;
456 #size-cells = <0>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_i2c1>;
462 clock-frequency = <100000>;
466 compatible = "socionext,uniphier-fi2c";
468 #address-cells = <1>;
469 #size-cells = <0>;
473 clock-frequency = <400000>;
477 compatible = "socionext,uniphier-fi2c";
480 #address-cells = <1>;
481 #size-cells = <0>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_i2c3>;
487 clock-frequency = <100000>;
491 compatible = "socionext,uniphier-fi2c";
494 #address-cells = <1>;
495 #size-cells = <0>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&pinctrl_i2c4>;
501 clock-frequency = <100000>;
505 compatible = "socionext,uniphier-fi2c";
507 #address-cells = <1>;
508 #size-cells = <0>;
512 clock-frequency = <400000>;
515 system_bus: system-bus@58c00000 {
516 compatible = "socionext,uniphier-system-bus";
519 #address-cells = <2>;
520 #size-cells = <1>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&pinctrl_system_bus>;
526 compatible = "socionext,uniphier-smpctrl";
531 compatible = "socionext,uniphier-ld20-sdctrl",
532 "simple-mfd", "syscon";
536 compatible = "socionext,uniphier-ld20-sd-clock";
537 #clock-cells = <1>;
541 compatible = "socionext,uniphier-ld20-sd-reset";
542 #reset-cells = <1>;
547 compatible = "socionext,uniphier-ld20-perictrl",
548 "simple-mfd", "syscon";
552 compatible = "socionext,uniphier-ld20-peri-clock";
553 #clock-cells = <1>;
557 compatible = "socionext,uniphier-ld20-peri-reset";
558 #reset-cells = <1>;
563 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_emmc>;
570 bus-width = <8>;
571 mmc-ddr-1_8v;
572 mmc-hs200-1_8v;
573 mmc-pwrseq = <&emmc_pwrseq>;
574 cdns,phy-input-delay-legacy = <9>;
575 cdns,phy-input-delay-mmc-highspeed = <2>;
576 cdns,phy-input-delay-mmc-ddr = <3>;
577 cdns,phy-dll-delay-sdclk = <21>;
578 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
582 compatible = "socionext,uniphier-sd-v3.1.1";
586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_sd>;
589 reset-names = "host";
591 bus-width = <4>;
592 cap-sd-highspeed;
595 soc_glue: soc-glue@5f800000 {
596 compatible = "socionext,uniphier-ld20-soc-glue",
597 "simple-mfd", "syscon";
601 compatible = "socionext,uniphier-ld20-pinctrl";
605 soc-glue@5f900000 {
606 compatible = "socionext,uniphier-ld20-soc-glue-debug",
607 "simple-mfd";
608 #address-cells = <1>;
609 #size-cells = <1>;
613 compatible = "socionext,uniphier-efuse";
618 compatible = "socionext,uniphier-efuse";
620 #address-cells = <1>;
621 #size-cells = <1>;
623 /* USB cells */
668 compatible = "socionext,uniphier-ld20-aidet";
670 interrupt-controller;
671 #interrupt-cells = <2>;
674 gic: interrupt-controller@5fe00000 {
675 compatible = "arm,gic-v3";
678 interrupt-controller;
679 #interrupt-cells = <3>;
684 compatible = "socionext,uniphier-ld20-sysctrl",
685 "simple-mfd", "syscon";
689 compatible = "socionext,uniphier-ld20-clock";
690 #clock-cells = <1>;
694 compatible = "socionext,uniphier-ld20-reset";
695 #reset-cells = <1>;
699 compatible = "socionext,uniphier-wdt";
703 compatible = "socionext,uniphier-ld20-thermal";
705 #thermal-sensor-cells = <0>;
706 socionext,tmod-calibration = <0x0f22 0x68ee>;
711 compatible = "socionext,uniphier-ld20-ave4";
715 pinctrl-names = "default";
716 pinctrl-0 = <&pinctrl_ether_rgmii>;
717 clock-names = "ether";
719 reset-names = "ether";
721 phy-mode = "rgmii";
722 local-mac-address = [00 00 00 00 00 00];
723 socionext,syscon-phy-mode = <&soc_glue 0>;
726 #address-cells = <1>;
727 #size-cells = <0>;
732 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
735 interrupt-names = "host";
737 pinctrl-names = "default";
738 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
740 clock-names = "ref", "bus_early", "suspend";
749 usb-glue@65b00000 {
750 compatible = "socionext,uniphier-ld20-dwc3-glue",
751 "simple-mfd";
752 #address-cells = <1>;
753 #size-cells = <1>;
757 compatible = "socionext,uniphier-ld20-usb3-reset";
759 #reset-cells = <1>;
760 clock-names = "link";
762 reset-names = "link";
767 compatible = "socionext,uniphier-ld20-usb3-regulator";
769 clock-names = "link";
771 reset-names = "link";
776 compatible = "socionext,uniphier-ld20-usb3-regulator";
778 clock-names = "link";
780 reset-names = "link";
785 compatible = "socionext,uniphier-ld20-usb3-regulator";
787 clock-names = "link";
789 reset-names = "link";
794 compatible = "socionext,uniphier-ld20-usb3-regulator";
796 clock-names = "link";
798 reset-names = "link";
802 usb_hsphy0: hs-phy@200 {
803 compatible = "socionext,uniphier-ld20-usb3-hsphy";
805 #phy-cells = <0>;
806 clock-names = "link", "phy";
808 reset-names = "link", "phy";
810 vbus-supply = <&usb_vbus0>;
811 nvmem-cell-names = "rterm", "sel_t", "hs_i";
812 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
816 usb_hsphy1: hs-phy@210 {
817 compatible = "socionext,uniphier-ld20-usb3-hsphy";
819 #phy-cells = <0>;
820 clock-names = "link", "phy";
822 reset-names = "link", "phy";
824 vbus-supply = <&usb_vbus1>;
825 nvmem-cell-names = "rterm", "sel_t", "hs_i";
826 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
830 usb_hsphy2: hs-phy@220 {
831 compatible = "socionext,uniphier-ld20-usb3-hsphy";
833 #phy-cells = <0>;
834 clock-names = "link", "phy";
836 reset-names = "link", "phy";
838 vbus-supply = <&usb_vbus2>;
839 nvmem-cell-names = "rterm", "sel_t", "hs_i";
840 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
844 usb_hsphy3: hs-phy@230 {
845 compatible = "socionext,uniphier-ld20-usb3-hsphy";
847 #phy-cells = <0>;
848 clock-names = "link", "phy";
850 reset-names = "link", "phy";
852 vbus-supply = <&usb_vbus3>;
853 nvmem-cell-names = "rterm", "sel_t", "hs_i";
854 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
858 usb_ssphy0: ss-phy@300 {
859 compatible = "socionext,uniphier-ld20-usb3-ssphy";
861 #phy-cells = <0>;
862 clock-names = "link", "phy";
864 reset-names = "link", "phy";
866 vbus-supply = <&usb_vbus0>;
869 usb_ssphy1: ss-phy@310 {
870 compatible = "socionext,uniphier-ld20-usb3-ssphy";
872 #phy-cells = <0>;
873 clock-names = "link", "phy";
875 reset-names = "link", "phy";
877 vbus-supply = <&usb_vbus1>;
882 compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
884 reg-names = "dbi", "link", "config";
887 #address-cells = <3>;
888 #size-cells = <2>;
891 num-lanes = <1>;
892 num-viewport = <1>;
893 bus-range = <0x0 0xff>;
898 /* non-prefetchable memory */
900 #interrupt-cells = <1>;
901 interrupt-names = "dma", "msi";
903 interrupt-map-mask = <0 0 0 7>;
904 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
908 phy-names = "pcie-phy";
911 pcie_intc: legacy-interrupt-controller {
912 interrupt-controller;
913 #interrupt-cells = <1>;
914 interrupt-parent = <&gic>;
920 compatible = "socionext,uniphier-ld20-pcie-phy";
922 #phy-cells = <0>;
929 compatible = "socionext,uniphier-denali-nand-v5b";
931 reg-names = "nand_data", "denali_reg";
933 #address-cells = <1>;
934 #size-cells = <0>;
936 pinctrl-names = "default";
937 pinctrl-0 = <&pinctrl_nand>;
938 clock-names = "nand", "nand_x", "ecc";
945 #include "uniphier-pinctrl.dtsi"
948 drive-strength = <4>; /* default: 3.5mA */
952 drive-strength = <5>; /* 5mA */
957 drive-strength = <4>; /* default: 3.5mA */
961 drive-strength = <11>; /* 11mA */