Lines Matching +full:psci +full:- +full:suspend +full:- +full:param
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
38 #address-cells = <2>;
39 #size-cells = <0>;
43 compatible = "arm,cortex-a35";
45 enable-method = "psci";
47 #cooling-cells = <2>;
48 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coefficient = <90>;
50 operating-points-v2 = <&cpu0_opp_table>;
55 compatible = "arm,cortex-a35";
57 enable-method = "psci";
59 #cooling-cells = <2>;
60 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coefficient = <90>;
62 operating-points-v2 = <&cpu0_opp_table>;
67 compatible = "arm,cortex-a35";
69 enable-method = "psci";
71 #cooling-cells = <2>;
72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coefficient = <90>;
74 operating-points-v2 = <&cpu0_opp_table>;
79 compatible = "arm,cortex-a35";
81 enable-method = "psci";
83 #cooling-cells = <2>;
84 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coefficient = <90>;
86 operating-points-v2 = <&cpu0_opp_table>;
89 idle-states {
90 entry-method = "psci";
92 CPU_SLEEP: cpu-sleep {
93 compatible = "arm,idle-state";
94 local-timer-stop;
95 arm,psci-suspend-param = <0x0010000>;
96 entry-latency-us = <120>;
97 exit-latency-us = <250>;
98 min-residency-us = <900>;
101 CLUSTER_SLEEP: cluster-sleep {
102 compatible = "arm,idle-state";
103 local-timer-stop;
104 arm,psci-suspend-param = <0x1010000>;
105 entry-latency-us = <400>;
106 exit-latency-us = <500>;
107 min-residency-us = <2000>;
112 cpu0_opp_table: cpu0-opp-table {
113 compatible = "operating-points-v2";
114 opp-shared;
116 opp-408000000 {
117 opp-hz = /bits/ 64 <408000000>;
118 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40000>;
120 opp-suspend;
122 opp-600000000 {
123 opp-hz = /bits/ 64 <600000000>;
124 opp-microvolt = <950000 950000 1350000>;
125 clock-latency-ns = <40000>;
127 opp-816000000 {
128 opp-hz = /bits/ 64 <816000000>;
129 opp-microvolt = <1050000 1050000 1350000>;
130 clock-latency-ns = <40000>;
132 opp-1008000000 {
133 opp-hz = /bits/ 64 <1008000000>;
134 opp-microvolt = <1175000 1175000 1350000>;
135 clock-latency-ns = <40000>;
137 opp-1200000000 {
138 opp-hz = /bits/ 64 <1200000000>;
139 opp-microvolt = <1300000 1300000 1350000>;
140 clock-latency-ns = <40000>;
142 opp-1296000000 {
143 opp-hz = /bits/ 64 <1296000000>;
144 opp-microvolt = <1350000 1350000 1350000>;
145 clock-latency-ns = <40000>;
149 arm-pmu {
150 compatible = "arm,cortex-a53-pmu";
155 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
158 display_subsystem: display-subsystem {
159 compatible = "rockchip,display-subsystem";
166 compatible = "linaro,optee-tz";
171 gmac_clkin: external-gmac-clock {
172 compatible = "fixed-clock";
173 clock-frequency = <50000000>;
174 clock-output-names = "gmac_clkin";
175 #clock-cells = <0>;
178 psci {
179 compatible = "arm,psci-1.0";
184 compatible = "arm,armv8-timer";
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <24000000>;
195 clock-output-names = "xin24m";
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <32768>;
202 clock-output-names = "xin32k";
205 pmu: power-management@ff000000 {
206 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
209 power: power-controller {
210 compatible = "rockchip,px30-power-controller";
211 #power-domain-cells = <1>;
212 #address-cells = <1>;
213 #size-cells = <0>;
293 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
295 #address-cells = <1>;
296 #size-cells = <1>;
298 pmu_io_domains: io-domains {
299 compatible = "rockchip,px30-pmu-io-voltage-domain";
303 reboot-mode {
304 compatible = "syscon-reboot-mode";
306 mode-bootloader = <BOOT_BL_DOWNLOAD>;
307 mode-fastboot = <BOOT_FASTBOOT>;
308 mode-loader = <BOOT_BL_DOWNLOAD>;
309 mode-normal = <BOOT_NORMAL>;
310 mode-recovery = <BOOT_RECOVERY>;
315 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
319 clock-names = "baudclk", "apb_pclk";
321 dma-names = "tx", "rx";
322 reg-shift = <2>;
323 reg-io-width = <4>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
330 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
334 clock-names = "i2s_clk", "i2s_hclk";
336 dma-names = "tx", "rx";
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
340 #sound-dai-cells = <0>;
345 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
349 clock-names = "i2s_clk", "i2s_hclk";
351 dma-names = "tx", "rx";
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
355 #sound-dai-cells = <0>;
359 gic: interrupt-controller@ff131000 {
360 compatible = "arm,gic-400";
361 #interrupt-cells = <3>;
362 #address-cells = <0>;
363 interrupt-controller;
373 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
375 #address-cells = <1>;
376 #size-cells = <1>;
378 io_domains: io-domains {
379 compatible = "rockchip,px30-io-voltage-domain";
385 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
389 clock-names = "baudclk", "apb_pclk";
391 dma-names = "tx", "rx";
392 reg-shift = <2>;
393 reg-io-width = <4>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
400 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
404 clock-names = "baudclk", "apb_pclk";
406 dma-names = "tx", "rx";
407 reg-shift = <2>;
408 reg-io-width = <4>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&uart2m0_xfer>;
415 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
419 clock-names = "baudclk", "apb_pclk";
421 dma-names = "tx", "rx";
422 reg-shift = <2>;
423 reg-io-width = <4>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
430 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
434 clock-names = "baudclk", "apb_pclk";
436 dma-names = "tx", "rx";
437 reg-shift = <2>;
438 reg-io-width = <4>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
445 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
449 clock-names = "baudclk", "apb_pclk";
451 dma-names = "tx", "rx";
452 reg-shift = <2>;
453 reg-io-width = <4>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
460 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
463 clock-names = "i2c", "pclk";
465 pinctrl-names = "default";
466 pinctrl-0 = <&i2c0_xfer>;
467 #address-cells = <1>;
468 #size-cells = <0>;
473 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
476 clock-names = "i2c", "pclk";
478 pinctrl-names = "default";
479 pinctrl-0 = <&i2c1_xfer>;
480 #address-cells = <1>;
481 #size-cells = <0>;
486 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
489 clock-names = "i2c", "pclk";
491 pinctrl-names = "default";
492 pinctrl-0 = <&i2c2_xfer>;
493 #address-cells = <1>;
494 #size-cells = <0>;
499 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
502 clock-names = "i2c", "pclk";
504 pinctrl-names = "default";
505 pinctrl-0 = <&i2c3_xfer>;
506 #address-cells = <1>;
507 #size-cells = <0>;
512 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
516 clock-names = "spiclk", "apb_pclk";
518 dma-names = "tx", "rx";
519 pinctrl-names = "default";
520 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
521 #address-cells = <1>;
522 #size-cells = <0>;
527 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
531 clock-names = "spiclk", "apb_pclk";
533 dma-names = "tx", "rx";
534 pinctrl-names = "default";
535 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
536 #address-cells = <1>;
537 #size-cells = <0>;
542 compatible = "snps,dw-wdt";
550 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
553 clock-names = "pwm", "pclk";
554 pinctrl-names = "default";
555 pinctrl-0 = <&pwm0_pin>;
556 #pwm-cells = <3>;
561 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
564 clock-names = "pwm", "pclk";
565 pinctrl-names = "default";
566 pinctrl-0 = <&pwm1_pin>;
567 #pwm-cells = <3>;
572 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
575 clock-names = "pwm", "pclk";
576 pinctrl-names = "default";
577 pinctrl-0 = <&pwm2_pin>;
578 #pwm-cells = <3>;
583 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
586 clock-names = "pwm", "pclk";
587 pinctrl-names = "default";
588 pinctrl-0 = <&pwm3_pin>;
589 #pwm-cells = <3>;
594 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
597 clock-names = "pwm", "pclk";
598 pinctrl-names = "default";
599 pinctrl-0 = <&pwm4_pin>;
600 #pwm-cells = <3>;
605 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
608 clock-names = "pwm", "pclk";
609 pinctrl-names = "default";
610 pinctrl-0 = <&pwm5_pin>;
611 #pwm-cells = <3>;
616 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
619 clock-names = "pwm", "pclk";
620 pinctrl-names = "default";
621 pinctrl-0 = <&pwm6_pin>;
622 #pwm-cells = <3>;
627 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
630 clock-names = "pwm", "pclk";
631 pinctrl-names = "default";
632 pinctrl-0 = <&pwm7_pin>;
633 #pwm-cells = <3>;
638 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
642 clock-names = "pclk", "timer";
646 compatible = "simple-bus";
647 #address-cells = <2>;
648 #size-cells = <2>;
657 clock-names = "apb_pclk";
658 #dma-cells = <1>;
663 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
666 #io-channel-cells = <1>;
668 clock-names = "saradc", "apb_pclk";
670 reset-names = "saradc-apb";
674 cru: clock-controller@ff2b0000 {
675 compatible = "rockchip,px30-cru";
678 #clock-cells = <1>;
679 #reset-cells = <1>;
681 assigned-clocks = <&cru PLL_NPLL>;
682 assigned-clock-rates = <1188000000>;
685 pmucru: clock-controller@ff2bc000 {
686 compatible = "rockchip,px30-pmucru";
689 #clock-cells = <1>;
690 #reset-cells = <1>;
692 assigned-clocks =
698 assigned-clock-rates =
707 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
712 clock-names = "otg";
714 g-np-tx-fifo-size = <16>;
715 g-rx-fifo-size = <280>;
716 g-tx-fifo-size = <256 128 128 64 32 16>;
717 g-use-dma;
718 power-domains = <&power PX30_PD_USB>;
723 compatible = "generic-ehci";
727 clock-names = "usbhost";
728 power-domains = <&power PX30_PD_USB>;
733 compatible = "generic-ohci";
737 clock-names = "usbhost";
738 power-domains = <&power PX30_PD_USB>;
743 compatible = "rockchip,px30-gmac";
746 interrupt-names = "macirq";
751 clock-names = "stmmaceth", "mac_clk_rx",
756 phy-mode = "rmii";
757 pinctrl-names = "default";
758 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
759 power-domains = <&power PX30_PD_GMAC>;
761 reset-names = "stmmaceth";
766 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
771 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
772 fifo-depth = <0x100>;
773 max-frequency = <150000000>;
774 pinctrl-names = "default";
775 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
776 power-domains = <&power PX30_PD_SDCARD>;
781 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
786 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
787 fifo-depth = <0x100>;
788 max-frequency = <150000000>;
789 pinctrl-names = "default";
790 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
791 power-domains = <&power PX30_PD_MMC_NAND>;
796 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
801 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
802 fifo-depth = <0x100>;
803 max-frequency = <150000000>;
804 power-domains = <&power PX30_PD_MMC_NAND>;
809 compatible = "rockchip,px30-vop-big";
814 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
816 reset-names = "axi", "ahb", "dclk";
818 power-domains = <&power PX30_PD_VO>;
823 #address-cells = <1>;
824 #size-cells = <0>;
832 interrupt-names = "vopb_mmu";
834 clock-names = "aclk", "hclk";
835 power-domains = <&power PX30_PD_VO>;
836 #iommu-cells = <0>;
841 compatible = "rockchip,px30-vop-lit";
846 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
848 reset-names = "axi", "ahb", "dclk";
850 power-domains = <&power PX30_PD_VO>;
855 #address-cells = <1>;
856 #size-cells = <0>;
864 interrupt-names = "vopl_mmu";
866 clock-names = "aclk", "hclk";
867 power-domains = <&power PX30_PD_VO>;
868 #iommu-cells = <0>;
973 compatible = "rockchip,px30-pinctrl";
976 #address-cells = <2>;
977 #size-cells = <2>;
981 compatible = "rockchip,gpio-bank";
985 gpio-controller;
986 #gpio-cells = <2>;
988 interrupt-controller;
989 #interrupt-cells = <2>;
993 compatible = "rockchip,gpio-bank";
997 gpio-controller;
998 #gpio-cells = <2>;
1000 interrupt-controller;
1001 #interrupt-cells = <2>;
1005 compatible = "rockchip,gpio-bank";
1009 gpio-controller;
1010 #gpio-cells = <2>;
1012 interrupt-controller;
1013 #interrupt-cells = <2>;
1017 compatible = "rockchip,gpio-bank";
1021 gpio-controller;
1022 #gpio-cells = <2>;
1024 interrupt-controller;
1025 #interrupt-cells = <2>;
1028 pcfg_pull_up: pcfg-pull-up {
1029 bias-pull-up;
1032 pcfg_pull_down: pcfg-pull-down {
1033 bias-pull-down;
1036 pcfg_pull_none: pcfg-pull-none {
1037 bias-disable;
1040 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1041 bias-disable;
1042 drive-strength = <2>;
1045 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1046 bias-pull-up;
1047 drive-strength = <2>;
1050 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1051 bias-pull-up;
1052 drive-strength = <4>;
1055 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1056 bias-disable;
1057 drive-strength = <4>;
1060 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1061 bias-pull-down;
1062 drive-strength = <4>;
1065 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1066 bias-disable;
1067 drive-strength = <8>;
1070 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1071 bias-pull-up;
1072 drive-strength = <8>;
1075 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1076 bias-disable;
1077 drive-strength = <12>;
1080 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1081 bias-pull-up;
1082 drive-strength = <12>;
1085 pcfg_pull_none_smt: pcfg-pull-none-smt {
1086 bias-disable;
1087 input-schmitt-enable;
1090 pcfg_output_high: pcfg-output-high {
1091 output-high;
1094 pcfg_output_low: pcfg-output-low {
1095 output-low;
1098 pcfg_input_high: pcfg-input-high {
1099 bias-pull-up;
1100 input-enable;
1103 pcfg_input: pcfg-input {
1104 input-enable;
1108 i2c0_xfer: i2c0-xfer {
1116 i2c1_xfer: i2c1-xfer {
1124 i2c2_xfer: i2c2-xfer {
1132 i2c3_xfer: i2c3-xfer {
1140 tsadc_otp_gpio: tsadc-otp-gpio {
1145 tsadc_otp_out: tsadc-otp-out {
1152 uart0_xfer: uart0-xfer {
1158 uart0_cts: uart0-cts {
1163 uart0_rts: uart0-rts {
1168 uart0_rts_gpio: uart0-rts-gpio {
1175 uart1_xfer: uart1-xfer {
1181 uart1_cts: uart1-cts {
1186 uart1_rts: uart1-rts {
1191 uart1_rts_gpio: uart1-rts-gpio {
1197 uart2-m0 {
1198 uart2m0_xfer: uart2m0-xfer {
1205 uart2-m1 {
1206 uart2m1_xfer: uart2m1-xfer {
1213 uart3-m0 {
1214 uart3m0_xfer: uart3m0-xfer {
1220 uart3m0_cts: uart3m0-cts {
1225 uart3m0_rts: uart3m0-rts {
1230 uart3m0_rts_gpio: uart3m0-rts-gpio {
1236 uart3-m1 {
1237 uart3m1_xfer: uart3m1-xfer {
1243 uart3m1_cts: uart3m1-cts {
1248 uart3m1_rts: uart3m1-rts {
1253 uart3m1_rts_gpio: uart3m1-rts-gpio {
1260 uart4_xfer: uart4-xfer {
1266 uart4_cts: uart4-cts {
1271 uart4_rts: uart4-rts {
1278 uart5_xfer: uart5-xfer {
1284 uart5_cts: uart5-cts {
1289 uart5_rts: uart5-rts {
1296 spi0_clk: spi0-clk {
1301 spi0_csn: spi0-csn {
1306 spi0_miso: spi0-miso {
1311 spi0_mosi: spi0-mosi {
1316 spi0_clk_hs: spi0-clk-hs {
1321 spi0_miso_hs: spi0-miso-hs {
1326 spi0_mosi_hs: spi0-mosi-hs {
1333 spi1_clk: spi1-clk {
1338 spi1_csn0: spi1-csn0 {
1343 spi1_csn1: spi1-csn1 {
1348 spi1_miso: spi1-miso {
1353 spi1_mosi: spi1-mosi {
1358 spi1_clk_hs: spi1-clk-hs {
1363 spi1_miso_hs: spi1-miso-hs {
1368 spi1_mosi_hs: spi1-mosi-hs {
1375 pdm_clk0m0: pdm-clk0m0 {
1380 pdm_clk0m1: pdm-clk0m1 {
1385 pdm_clk1: pdm-clk1 {
1390 pdm_sdi0m0: pdm-sdi0m0 {
1395 pdm_sdi0m1: pdm-sdi0m1 {
1400 pdm_sdi1: pdm-sdi1 {
1405 pdm_sdi2: pdm-sdi2 {
1410 pdm_sdi3: pdm-sdi3 {
1415 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1420 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1425 pdm_clk1_sleep: pdm-clk1-sleep {
1430 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1435 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1440 pdm_sdi1_sleep: pdm-sdi1-sleep {
1445 pdm_sdi2_sleep: pdm-sdi2-sleep {
1450 pdm_sdi3_sleep: pdm-sdi3-sleep {
1457 i2s0_8ch_mclk: i2s0-8ch-mclk {
1462 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1467 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1472 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1477 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1482 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1487 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1492 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1497 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1502 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1507 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1512 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1517 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1524 i2s1_2ch_mclk: i2s1-2ch-mclk {
1529 i2s1_2ch_sclk: i2s1-2ch-sclk {
1534 i2s1_2ch_lrck: i2s1-2ch-lrck {
1539 i2s1_2ch_sdi: i2s1-2ch-sdi {
1544 i2s1_2ch_sdo: i2s1-2ch-sdo {
1551 i2s2_2ch_mclk: i2s2-2ch-mclk {
1556 i2s2_2ch_sclk: i2s2-2ch-sclk {
1561 i2s2_2ch_lrck: i2s2-2ch-lrck {
1566 i2s2_2ch_sdi: i2s2-2ch-sdi {
1571 i2s2_2ch_sdo: i2s2-2ch-sdo {
1578 sdmmc_clk: sdmmc-clk {
1583 sdmmc_cmd: sdmmc-cmd {
1588 sdmmc_det: sdmmc-det {
1593 sdmmc_bus1: sdmmc-bus1 {
1598 sdmmc_bus4: sdmmc-bus4 {
1606 sdmmc_gpio: sdmmc-gpio {
1618 sdio_clk: sdio-clk {
1623 sdio_cmd: sdio-cmd {
1628 sdio_bus4: sdio-bus4 {
1636 sdio_gpio: sdio-gpio {
1648 emmc_clk: emmc-clk {
1653 emmc_cmd: emmc-cmd {
1658 emmc_pwren: emmc-pwren {
1663 emmc_rstnout: emmc-rstnout {
1668 emmc_bus1: emmc-bus1 {
1673 emmc_bus4: emmc-bus4 {
1681 emmc_bus8: emmc-bus8 {
1695 flash_cs0: flash-cs0 {
1700 flash_rdy: flash-rdy {
1705 flash_dqs: flash-dqs {
1710 flash_ale: flash-ale {
1715 flash_cle: flash-cle {
1720 flash_wrn: flash-wrn {
1725 flash_csl: flash-csl {
1730 flash_rdn: flash-rdn {
1735 flash_bus8: flash-bus8 {
1749 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1754 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1759 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1764 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1769 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
1797 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
1819 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
1839 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
1860 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
1875 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
1890 pwm0_pin: pwm0-pin {
1897 pwm1_pin: pwm1-pin {
1904 pwm2_pin: pwm2-pin {
1911 pwm3_pin: pwm3-pin {
1918 pwm4_pin: pwm4-pin {
1925 pwm5_pin: pwm5-pin {
1932 pwm6_pin: pwm6-pin {
1939 pwm7_pin: pwm7-pin {
1946 rmii_pins: rmii-pins {
1959 mac_refclk_12ma: mac-refclk-12ma {
1964 mac_refclk: mac-refclk {
1970 cif-m0 {
1971 cif_clkout_m0: cif-clkout-m0 {
1976 dvp_d2d9_m0: dvp-d2d9-m0 {
1992 dvp_d0d1_m0: dvp-d0d1-m0 {
1998 dvp_d10d11_m0:d10-d11-m0 {
2005 cif-m1 {
2006 cif_clkout_m1: cif-clkout-m1 {
2011 dvp_d2d9_m1: dvp-d2d9-m1 {
2027 dvp_d0d1_m1: dvp-d0d1-m1 {
2033 dvp_d10d11_m1:d10-d11-m1 {
2041 isp_prelight: isp-prelight {